From: Daniel Sanders <daniel.sanders@imgtec.com>
Date: Mon, 30 Mar 2015 13:47:23 +0000 (+0000)
Subject: [mips] Add support for 'ZC' inline assembly memory constraint.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=822a5e36ffeb3a1893363d1364af6284f2ab7064;p=clang

[mips] Add support for 'ZC' inline assembly memory constraint.

Summary: Also add tests for 'R' and 'm'.

Reviewers: atanasyan

Reviewed By: atanasyan

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D8449

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@233542 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index c8fa0cce25..7cb6480c2c 100644
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -5857,7 +5857,28 @@ public:
     case 'R': // An address that can be used in a non-macro load or store
       Info.setAllowsMemory();
       return true;
+    case 'Z':
+      if (Name[1] == 'C') { // An address usable by ll, and sc.
+        Info.setAllowsMemory();
+        Name++; // Skip over 'Z'.
+        return true;
+      }
+      return false;
+    }
+  }
+
+  std::string convertConstraint(const char *&Constraint) const override {
+    std::string R;
+    switch (*Constraint) {
+    case 'Z': // Two-character constraint; add "^" hint for later parsing.
+      if (Constraint[1] == 'C') {
+        R = std::string("^") + std::string(Constraint, 2);
+        Constraint++;
+        return R;
+      }
+      break;
     }
+    return TargetInfo::convertConstraint(Constraint);
   }
 
   const char *getClobbers() const override {
diff --git a/test/CodeGen/mips-inline-asm.c b/test/CodeGen/mips-inline-asm.c
new file mode 100644
index 0000000000..2cfa41c98d
--- /dev/null
+++ b/test/CodeGen/mips-inline-asm.c
@@ -0,0 +1,19 @@
+// REQUIRES: mips-registered-target
+// RUN: %clang_cc1 -triple mips-linux-gnu -emit-llvm -o - %s | FileCheck %s
+
+int data;
+
+void m () {
+  asm("lw $1, %0" :: "m"(data));
+  // CHECK: call void asm sideeffect "lw $$1, $0", "*m,~{$1}"(i32* @data)
+}
+
+void ZC () {
+  asm("ll $1, %0" :: "ZC"(data));
+  // CHECK: call void asm sideeffect "ll $$1, $0", "*^ZC,~{$1}"(i32* @data)
+}
+
+void R () {
+  asm("lw $1, %0" :: "R"(data));
+  // CHECK: call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* @data)
+}