From: Amara Emerson <amara.emerson@arm.com>
Date: Mon, 7 Nov 2016 15:42:12 +0000 (+0000)
Subject: This patch adds support for 16 bit floating point registers to the inline asm registe... 
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=813d12083c3e6f4f68a931e6b6c1166b13ca7c6c;p=llvm

This patch adds support for 16 bit floating point registers to the inline asm register selection on AArch64.

Without this patch, register allocation for the example below fails.

define half @test(half %a1, half %a2) #0 {
entry:
  %0 = tail call half asm "sqrshl ${0:h}, ${1:h}, ${2:h}", "=w,w,w" (half %a1, half %a2) #1
  ret half %0
}

Patch by Florian Hahn.

Differential Revision: https://reviews.llvm.org/D25080



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286111 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp
index 076145c36b2..04219baf041 100644
--- a/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -4780,6 +4780,8 @@ AArch64TargetLowering::getRegForInlineAsmConstraint(
         return std::make_pair(0U, &AArch64::GPR64commonRegClass);
       return std::make_pair(0U, &AArch64::GPR32commonRegClass);
     case 'w':
+      if (VT.getSizeInBits() == 16)
+        return std::make_pair(0U, &AArch64::FPR16RegClass);
       if (VT.getSizeInBits() == 32)
         return std::make_pair(0U, &AArch64::FPR32RegClass);
       if (VT.getSizeInBits() == 64)
diff --git a/test/CodeGen/AArch64/neon-inline-asm-16-bit-fp.ll b/test/CodeGen/AArch64/neon-inline-asm-16-bit-fp.ll
new file mode 100644
index 00000000000..3656a787977
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-inline-asm-16-bit-fp.ll
@@ -0,0 +1,20 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+
+; generated from
+; __fp16 test(__fp16 a1, __fp16 a2) {
+;    __fp16 res0;
+;    __asm__("sqrshl %h[__res], %h[__A], %h[__B]"
+;             : [__res] "=w" (res0)
+;             : [__A] "w" (a1), [__B] "w" (a2)
+;             :
+;             );
+;    return res0;
+;}
+
+; Function Attrs: nounwind readnone
+define half @test(half %a1, half %a2) #0 {
+entry:
+  ;CHECK: sqrshl {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
+  %0 = tail call half asm "sqrshl ${0:h}, ${1:h}, ${2:h}", "=w,w,w" (half %a1, half %a2) #1
+  ret half %0
+}