From: Sjoerd Meijer <sjoerd.meijer@arm.com>
Date: Mon, 18 Sep 2017 14:17:57 +0000 (+0000)
Subject: [ARM] Fix for indexed dot product instruction descriptions
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=80ee0e02a2ad286f73559b380da660dbff86c6b4;p=llvm

[ARM] Fix for indexed dot product instruction descriptions

The indexed dot product instructions only accept the lower 16 D-registers as
the indexed register, but we were e.g. incorrectly accepting:

vudot.u8 d16,d16,d18[0]

Differential Revision: https://reviews.llvm.org/D37968


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313531 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index 9c729bd2c9f..86c90efce2c 100644
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -4710,7 +4710,7 @@ def VSDOTQ : N3Vnp<0b11000, 0b10, 0b1101, 0b1, 0b0,
 // Indexed dot product instructions:
 class DOTI<string opc, string dt, bit Q, bit U, RegisterClass Ty> :
   N3Vnp<0b11100, 0b10, 0b1101, Q, U,
-       (outs Ty:$Vd), (ins Ty:$Vn, DPR:$Vm, VectorIndex32:$lane),
+       (outs Ty:$Vd), (ins Ty:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
        N3RegFrm, IIC_VDOTPROD, opc, dt, []> {
   bit lane;
   let Inst{5} = lane;
diff --git a/test/MC/ARM/armv8.2a-dotprod-error.s b/test/MC/ARM/armv8.2a-dotprod-error.s
index 424fa5a12c9..c8497c30a00 100644
--- a/test/MC/ARM/armv8.2a-dotprod-error.s
+++ b/test/MC/ARM/armv8.2a-dotprod-error.s
@@ -3,12 +3,34 @@
 // RUN: not llvm-mc -triple thumb -mattr=+dotprod -show-encoding < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
 
+// Only indices 0 an 1 should be accepted:
+
 vudot.u8 d0, d1, d2[2]
 vsdot.s8 d0, d1, d2[2]
 vudot.u8 q0, q1, d4[2]
 vsdot.s8 q0, q1, d4[2]
 
 // CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: vudot.u8 d0, d1, d2[2]
+// CHECK-ERROR:                    ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: vsdot.s8 d0, d1, d2[2]
+// CHECK-ERROR:                    ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: vudot.u8 q0, q1, d4[2]
+// CHECK-ERROR:                    ^
 // CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: vsdot.s8 q0, q1, d4[2]
+// CHECK-ERROR:                    ^
+
+// Only the lower 16 D-registers should be accepted:
+
+vudot.u8 q0, q1, d16[0]
+vsdot.s8 q0, q1, d16[0]
+
 // CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: vudot.u8 q0, q1, d16[0]
+// CHECK-ERROR:                     ^
 // CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR: vsdot.s8 q0, q1, d16[0]
+// CHECK-ERROR:                     ^