From: Sanjoy Das <sanjoy@playingwithpointers.com>
Date: Mon, 19 Jun 2017 22:35:48 +0000 (+0000)
Subject: Fix machine instruction in test case
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=7ef9a64157c5871d47b14aa0cc76aff0b49f3739;p=llvm

Fix machine instruction in test case

The AMD64rm instruction used in the test case was incorrect.  Since
the first input register to AND64rm is tied to output register, they
must be the same.

Thanks for Jesper Antonsson for pointing this out!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305756 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/X86/implicit-null-checks.mir b/test/CodeGen/X86/implicit-null-checks.mir
index b05c4467d30..6efc965a694 100644
--- a/test/CodeGen/X86/implicit-null-checks.mir
+++ b/test/CodeGen/X86/implicit-null-checks.mir
@@ -544,7 +544,7 @@ liveins:
   - { reg: '%rsi' }
 # CHECK:  bb.0.entry:
 # CHECK:  %rbx = MOV64rr %rdx
-# CHECK-NEXT:  %rdi = FAULTING_OP 1, %bb.3.is_null, {{[0-9]+}}, %rbx, %rdi, 1, _, 0, _, implicit-def %eflags :: (load 4 from %ir.x)
+# CHECK-NEXT:  %rbx = FAULTING_OP 1, %bb.3.is_null, {{[0-9]+}}, %rbx, %rdi, 1, _, 0, _, implicit-def %eflags :: (load 4 from %ir.x)
 
 body:             |
   bb.0.entry:
@@ -557,9 +557,9 @@ body:             |
     liveins: %rsi, %rdi, %rdx
 
     %rbx  = MOV64rr %rdx
-    %rdi = AND64rm killed %rbx, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
+    %rbx = AND64rm killed %rbx, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x)
     %rdx = MOV64ri 0
-    CMP64rr killed %rdi, killed %rsi, implicit-def %eflags
+    CMP64rr killed %rbx, killed %rsi, implicit-def %eflags
     JE_1 %bb.4.ret_100, implicit %eflags
 
   bb.2.ret_200: