From: Chen Zheng <czhengsz@cn.ibm.com>
Date: Wed, 30 Jan 2019 23:18:38 +0000 (+0000)
Subject: [PowerPC] delete no more needed workaround for readsRegister() in PowerPC
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=7ecd40e2fe2190e3b808376ff82e8aa5523a9911;p=llvm

[PowerPC] delete no more needed workaround for readsRegister() in PowerPC
Differential Revision: https://reviews.llvm.org/D57439


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352689 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index ecc5e28c0d8..5952d73d205 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2357,13 +2357,6 @@ MachineInstr *PPCInstrInfo::getForwardingDefMI(
         MachineBasicBlock::reverse_iterator E = MI.getParent()->rend(), It = MI;
         It++;
         unsigned Reg = MI.getOperand(i).getReg();
-        // MachineInstr::readsRegister only returns true if the machine
-        // instruction reads the exact register or its super-register. It
-        // does not consider uses of sub-registers which seems like strange
-        // behaviour. Nonetheless, if we end up with a 64-bit register here,
-        // get the corresponding 32-bit register to check.
-        if (PPC::G8RCRegClass.contains(Reg))
-          Reg = Reg - PPC::X0 + PPC::R0;
 
         // Is this register defined by some form of add-immediate (including
         // load-immediate) within this basic block?
@@ -3183,14 +3176,7 @@ bool PPCInstrInfo::isRegElgibleForForwarding(const MachineOperand &RegMO,
   if (MRI.isSSA())
     return false;
 
-  // MachineInstr::readsRegister only returns true if the machine
-  // instruction reads the exact register or its super-register. It
-  // does not consider uses of sub-registers which seems like strange
-  // behaviour. Nonetheless, if we end up with a 64-bit register here,
-  // get the corresponding 32-bit register to check.
   unsigned Reg = RegMO.getReg();
-  if (PPC::G8RCRegClass.contains(Reg))
-    Reg = Reg - PPC::X0 + PPC::R0;
 
   // Walking the inst in reverse(MI-->DefMI) to get the last DEF of the Reg.
   MachineBasicBlock::const_reverse_iterator It = MI;
diff --git a/test/CodeGen/PowerPC/convert-rr-to-ri-instr-add.mir b/test/CodeGen/PowerPC/convert-rr-to-ri-instr-add.mir
index 420f1f58b68..b92884ae9b4 100644
--- a/test/CodeGen/PowerPC/convert-rr-to-ri-instr-add.mir
+++ b/test/CodeGen/PowerPC/convert-rr-to-ri-instr-add.mir
@@ -15,3 +15,21 @@ body: |
     ; CHECK: STD killed $x3, killed $x5, 100
     BLR8 implicit $lr8, implicit $rm
 ...
+---
+# No workaround needed for 64-bit register when calling readsRegister()
+name: testReadsSubRegADDI
+# CHECK: name: testReadsSubRegADDI
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3, $f1, $x5
+    $x3 = ADDI8 $x5, 100
+    ; Following instruction $r3 also reads $x3, ADDI8 can not be erased
+    ; CHECK: $x3 = ADDI8 $x5, 100, implicit-def $r3
+    STW $r3, $x5, 100
+    ; CHECK: STW $r3, $x5, 100
+    STFSX killed $f1, $zero8, $x3
+    ; CHECK: STFS killed $f1, 100, $x5
+    STD $x5, $x5, 100
+    BLR8 implicit $lr8, implicit $rm
+...