From: Michael Zuckerman <Michael.zuckerman@intel.com>
Date: Mon, 2 May 2016 07:35:27 +0000 (+0000)
Subject: [Clang][BuiltIn][avx512] Adding intrinsics for vpshufd instruction set
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=7dcd386b4f7b7f92ccc2c4d2ee01d4aa906ef325;p=clang

[Clang][BuiltIn][avx512] Adding intrinsics for vpshufd instruction set

Differential Revision: http://reviews.llvm.org/D19580




git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@268213 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/clang/Basic/BuiltinsX86.def b/include/clang/Basic/BuiltinsX86.def
index 429f25a27d..d50006a602 100644
--- a/include/clang/Basic/BuiltinsX86.def
+++ b/include/clang/Basic/BuiltinsX86.def
@@ -2230,6 +2230,9 @@ TARGET_BUILTIN(__builtin_ia32_movshdup128_mask, "V4fV4fV4fUc","","avx512vl")
 TARGET_BUILTIN(__builtin_ia32_movshdup256_mask, "V8fV8fV8fUc","","avx512vl")
 TARGET_BUILTIN(__builtin_ia32_movsldup128_mask, "V4fV4fV4fUc","","avx512vl")
 TARGET_BUILTIN(__builtin_ia32_movsldup256_mask, "V8fV8fV8fUc","","avx512vl")
+TARGET_BUILTIN(__builtin_ia32_pshufd512_mask, "V16iV16iCsV16iUc","","avx512f")
+TARGET_BUILTIN(__builtin_ia32_pshufd256_mask, "V8iV8iCsV8iUc","","avx512vl")
+TARGET_BUILTIN(__builtin_ia32_pshufd128_mask, "V4iV4iCsV4iUc","","avx512vl")
 
 #undef BUILTIN
 #undef TARGET_BUILTIN
diff --git a/lib/Headers/avx512fintrin.h b/lib/Headers/avx512fintrin.h
index 9292a289dc..651e1c0047 100644
--- a/lib/Headers/avx512fintrin.h
+++ b/lib/Headers/avx512fintrin.h
@@ -7733,6 +7733,27 @@ _mm512_maskz_moveldup_ps (__mmask16 __U, __m512 __A)
                (__mmask16) __U);
 }
 
+#define _mm512_shuffle_epi32( __A, __I) __extension__ ({ \
+__builtin_ia32_pshufd512_mask ((__v16si)( __A),\
+              ( __I),\
+              (__v16si) _mm512_undefined_epi32 (),\
+              (__mmask16) -1);\
+})
+
+#define _mm512_mask_shuffle_epi32( __W, __U, __A, __I) __extension__ ({ \
+__builtin_ia32_pshufd512_mask ((__v16si)( __A),\
+              ( __I),\
+              (__v16si)( __W),\
+              (__mmask16)( __U));\
+})
+
+#define _mm512_maskz_shuffle_epi32( __U, __A, __I) __extension__ ({ \
+__builtin_ia32_pshufd512_mask ((__v16si)( __A),\
+              ( __I),\
+              (__v16si) _mm512_setzero_si512 (),\
+              (__mmask16)( __U));\
+})
+
 #undef __DEFAULT_FN_ATTRS
 
 #endif // __AVX512FINTRIN_H
diff --git a/lib/Headers/avx512vlintrin.h b/lib/Headers/avx512vlintrin.h
index e4d95c28f3..3aacc68b0a 100644
--- a/lib/Headers/avx512vlintrin.h
+++ b/lib/Headers/avx512vlintrin.h
@@ -9361,6 +9361,29 @@ _mm256_maskz_moveldup_ps (__mmask8 __U, __m256 __A)
                (__mmask8) __U);
 }
 
+#define _mm256_mask_shuffle_epi32( __W, __U, __A, __I) __extension__({\
+__builtin_ia32_pshufd256_mask((__v8si) (__A), (__I),\
+              (__v8si) (__W), (__mmask8) __U);\
+})
+
+#define _mm256_maskz_shuffle_epi32( __U,  __A, __I) __extension__({\
+__builtin_ia32_pshufd256_mask((__v8si) (__A), (__I),\
+              (__v8si) _mm256_setzero_si256 (),\
+              (__mmask8) (__U));\
+})
+
+#define _mm_mask_shuffle_epi32( __W, __U, __A, __I) __extension__({\
+  __builtin_ia32_pshufd128_mask ((__v4si) (__A), (__I),\
+              (__v4si) (__W), (__mmask8) __U);\
+})
+
+#define _mm_maskz_shuffle_epi32( __U,  __A, __I) __extension__({\
+  __builtin_ia32_pshufd128_mask ((__v4si) (__A), (__I),\
+              (__v4si)\
+              _mm_setzero_si128 (),\
+              (__mmask8) (__U));\
+})
+
 #undef __DEFAULT_FN_ATTRS
 #undef __DEFAULT_FN_ATTRS_BOTH
 
diff --git a/test/CodeGen/avx512f-builtins.c b/test/CodeGen/avx512f-builtins.c
index 137aa91c55..b1b9c9b94b 100644
--- a/test/CodeGen/avx512f-builtins.c
+++ b/test/CodeGen/avx512f-builtins.c
@@ -5369,3 +5369,22 @@ __m512 test_mm512_maskz_moveldup_ps(__mmask16 __U, __m512 __A) {
   // CHECK: @llvm.x86.avx512.mask.movsldup.512
   return _mm512_maskz_moveldup_ps(__U, __A); 
 }
+
+__m512i test_mm512_shuffle_epi32(__m512i __A) {
+  // CHECK-LABEL: @test_mm512_shuffle_epi32
+  // CHECK: @llvm.x86.avx512.mask.pshuf.d.512
+  return _mm512_shuffle_epi32(__A, 1); 
+}
+
+__m512i test_mm512_mask_shuffle_epi32(__m512i __W, __mmask16 __U, __m512i __A) {
+  // CHECK-LABEL: @test_mm512_mask_shuffle_epi32
+  // CHECK: @llvm.x86.avx512.mask.pshuf.d.512
+  return _mm512_mask_shuffle_epi32(__W, __U, __A, 1); 
+}
+
+__m512i test_mm512_maskz_shuffle_epi32(__mmask16 __U, __m512i __A) {
+  // CHECK-LABEL: @test_mm512_maskz_shuffle_epi32
+  // CHECK: @llvm.x86.avx512.mask.pshuf.d.512
+  return _mm512_maskz_shuffle_epi32(__U, __A, 1); 
+}
+
diff --git a/test/CodeGen/avx512vl-builtins.c b/test/CodeGen/avx512vl-builtins.c
index d9d3f7a063..3ab3d94299 100644
--- a/test/CodeGen/avx512vl-builtins.c
+++ b/test/CodeGen/avx512vl-builtins.c
@@ -6581,3 +6581,28 @@ __m256 test_mm256_maskz_moveldup_ps(__mmask8 __U, __m256 __A) {
   // CHECK: @llvm.x86.avx512.mask.movsldup.256
   return _mm256_maskz_moveldup_ps(__U, __A); 
 }
+
+__m128i test_mm_mask_shuffle_epi32(__m128i __W, __mmask8 __U, __m128i __A) {
+  // CHECK-LABEL: @test_mm_mask_shuffle_epi32
+  // CHECK: @llvm.x86.avx512.mask.pshuf.d.128
+  return _mm_mask_shuffle_epi32(__W, __U, __A, 1); 
+}
+
+__m128i test_mm_maskz_shuffle_epi32(__mmask8 __U, __m128i __A) {
+  // CHECK-LABEL: @test_mm_maskz_shuffle_epi32
+  // CHECK: @llvm.x86.avx512.mask.pshuf.d.128
+  return _mm_maskz_shuffle_epi32(__U, __A, 2); 
+}
+
+__m256i test_mm256_mask_shuffle_epi32(__m256i __W, __mmask8 __U, __m256i __A) {
+  // CHECK-LABEL: @test_mm256_mask_shuffle_epi32
+  // CHECK: @llvm.x86.avx512.mask.pshuf.d.256
+  return _mm256_mask_shuffle_epi32(__W, __U, __A, 2); 
+}
+
+__m256i test_mm256_maskz_shuffle_epi32(__mmask8 __U, __m256i __A) {
+  // CHECK-LABEL: @test_mm256_maskz_shuffle_epi32
+  // CHECK: @llvm.x86.avx512.mask.pshuf.d.256
+  return _mm256_maskz_shuffle_epi32(__U, __A, 2); 
+}
+