From: Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>
Date: Mon, 19 Jun 2017 23:17:36 +0000 (+0000)
Subject: [AMDGPU] Add infer address spaces pass before SROA
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=7c44c2a308cdb9db4b11c5fef0bebe61f98a9069;p=llvm

[AMDGPU] Add infer address spaces pass before SROA

It adds it for the target after inlining but before SROA where
we can get most out of it.

Differential Revision: https://reviews.llvm.org/D34366

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305759 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index b644eba536f..04fe9f68980 100644
--- a/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -342,6 +342,14 @@ void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
         PM.add(createAMDGPUExternalAAWrapperPass());
       }
   });
+
+  Builder.addExtension(
+    PassManagerBuilder::EP_CGSCCOptimizerLate,
+    [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
+      // Add infer address spaces pass to the opt pipeline after inlining
+      // but before SROA to increase SROA opportunities.
+      PM.add(createInferAddressSpacesPass());
+  });
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/test/CodeGen/AMDGPU/infer-addrpace-pipeline.ll b/test/CodeGen/AMDGPU/infer-addrpace-pipeline.ll
new file mode 100644
index 00000000000..912b5ea949d
--- /dev/null
+++ b/test/CodeGen/AMDGPU/infer-addrpace-pipeline.ll
@@ -0,0 +1,10 @@
+; RUN: opt -mtriple=amdgcn--amdhsa -disable-output -disable-verify -debug-pass=Structure -O2 %s 2>&1 | FileCheck -check-prefix=GCN %s
+
+; GCN: Function Integration/Inlining
+; GCN: FunctionPass Manager
+; GCN: Infer address spaces
+; GCN: SROA
+
+define void @empty() {
+  ret void
+}