From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Thu, 10 Nov 2016 21:57:42 +0000 (+0000)
Subject: [SelectionDAG] Add support for splatted vectors in SUB opcode
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=7a98835990cd3e32fa43a214312492aa8f5e68da;p=llvm

[SelectionDAG] Add support for splatted vectors in SUB opcode

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286509 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 15dbacdfb4a..446067aeb8d 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2414,7 +2414,7 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
     break;
 
   case ISD::SUB: {
-    if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
+    if (ConstantSDNode *CLHS = isConstOrConstSplat(Op.getOperand(0))) {
       // We know that the top bits of C-X are clear if X contains less bits
       // than C (i.e. no wrap-around can happen).  For example, 20-X is
       // positive if we can prove that X is >= 0 and < 16.
diff --git a/test/CodeGen/X86/known-bits-vector.ll b/test/CodeGen/X86/known-bits-vector.ll
index 7cc6bfb3745..d7f27382e8b 100644
--- a/test/CodeGen/X86/known-bits-vector.ll
+++ b/test/CodeGen/X86/known-bits-vector.ll
@@ -207,18 +207,12 @@ define <4 x i32> @knownbits_mask_trunc_shuffle_shl(<4 x i64> %a0) nounwind {
 define <4 x i32> @knownbits_sub_lshr(<4 x i32> %a0) nounwind {
 ; X32-LABEL: knownbits_sub_lshr:
 ; X32:       # BB#0:
-; X32-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
-; X32-NEXT:    vmovdqa {{.*#+}} xmm1 = [255,255,255,255]
-; X32-NEXT:    vpsubd %xmm0, %xmm1, %xmm0
-; X32-NEXT:    vpsrld $22, %xmm0, %xmm0
+; X32-NEXT:    vxorps %xmm0, %xmm0, %xmm0
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: knownbits_sub_lshr:
 ; X64:       # BB#0:
-; X64-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
-; X64-NEXT:    vmovdqa {{.*#+}} xmm1 = [255,255,255,255]
-; X64-NEXT:    vpsubd %xmm0, %xmm1, %xmm0
-; X64-NEXT:    vpsrld $22, %xmm0, %xmm0
+; X64-NEXT:    vxorps %xmm0, %xmm0, %xmm0
 ; X64-NEXT:    retq
   %1 = and <4 x i32> %a0, <i32 15, i32 15, i32 15, i32 15>
   %2 = sub <4 x i32> <i32 255, i32 255, i32 255, i32 255>, %1