From: Peter Johnson <peter@tortall.net>
Date: Tue, 21 Oct 2003 01:36:19 +0000 (-0000)
Subject: Fix a couple of MMX/SSE/SSE2 instructions: movntps, movntq, movss, and the
X-Git-Tag: v0.4.0~93
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=7a1ed5ff15e9093a466ef347e6220ca2a5b3e637;p=yasm

Fix a couple of MMX/SSE/SSE2 instructions: movntps, movntq, movss, and the
pcmp* family.  The first three had some operand encoding problems, and pcmp*
was typoed as pacmp*.
Reported by: Edouard Gomez <ed.gomez@free.fr>

svn path=/trunk/yasm/; revision=1072
---

diff --git a/modules/arch/x86/tests/Makefile.inc b/modules/arch/x86/tests/Makefile.inc
index 24f4dd68..65dd2038 100644
--- a/modules/arch/x86/tests/Makefile.inc
+++ b/modules/arch/x86/tests/Makefile.inc
@@ -98,6 +98,9 @@ EXTRA_DIST += modules/arch/x86/tests/segmov.hex
 EXTRA_DIST += modules/arch/x86/tests/shift.asm
 EXTRA_DIST += modules/arch/x86/tests/shift.errwarn
 EXTRA_DIST += modules/arch/x86/tests/shift.hex
+EXTRA_DIST += modules/arch/x86/tests/simd-1.asm
+EXTRA_DIST += modules/arch/x86/tests/simd-1.errwarn
+EXTRA_DIST += modules/arch/x86/tests/simd-1.hex
 EXTRA_DIST += modules/arch/x86/tests/stos.asm
 EXTRA_DIST += modules/arch/x86/tests/stos.errwarn
 EXTRA_DIST += modules/arch/x86/tests/stos.hex
diff --git a/modules/arch/x86/tests/simd-1.asm b/modules/arch/x86/tests/simd-1.asm
new file mode 100644
index 00000000..0b752d93
--- /dev/null
+++ b/modules/arch/x86/tests/simd-1.asm
@@ -0,0 +1,11 @@
+[bits 32]
+movntps [0], xmm4
+movntps dqword [0], xmm5
+movntq [8], mm6
+movntq qword [8], mm7
+movss xmm0, [0]
+movss xmm1, dword [8]
+movss [0], xmm2
+movss dword [8], xmm3
+pcmpeqb xmm3, xmm4
+pcmpgtw mm0, mm2
diff --git a/modules/arch/x86/tests/simd-1.errwarn b/modules/arch/x86/tests/simd-1.errwarn
new file mode 100644
index 00000000..e69de29b
diff --git a/modules/arch/x86/tests/simd-1.hex b/modules/arch/x86/tests/simd-1.hex
new file mode 100644
index 00000000..2f564c7b
--- /dev/null
+++ b/modules/arch/x86/tests/simd-1.hex
@@ -0,0 +1,67 @@
+0f 
+2b 
+25 
+00 
+00 
+00 
+00 
+0f 
+2b 
+2d 
+00 
+00 
+00 
+00 
+0f 
+e7 
+35 
+08 
+00 
+00 
+00 
+0f 
+e7 
+3d 
+08 
+00 
+00 
+00 
+f3 
+0f 
+10 
+05 
+00 
+00 
+00 
+00 
+f3 
+0f 
+10 
+0d 
+08 
+00 
+00 
+00 
+f3 
+0f 
+11 
+15 
+00 
+00 
+00 
+00 
+f3 
+0f 
+11 
+1d 
+08 
+00 
+00 
+00 
+66 
+0f 
+74 
+dc 
+0f 
+65 
+c2 
diff --git a/modules/arch/x86/x86id.re b/modules/arch/x86/x86id.re
index 7f5cbe64..fa3c9c05 100644
--- a/modules/arch/x86/x86id.re
+++ b/modules/arch/x86/x86id.re
@@ -1347,19 +1347,19 @@ static const x86_insn_info movmskps_insn[] = {
 };
 static const x86_insn_info movntps_insn[] = {
     { CPU_SSE, 0, 0, 0, 2, {0x0F, 0x2B, 0}, 0, 2,
-      {OPT_Mem|OPS_128|OPS_Relaxed|OPA_EA, OPT_Reg|OPS_128|OPA_Spare, 0} }
+      {OPT_Mem|OPS_128|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
 };
 static const x86_insn_info movntq_insn[] = {
     { CPU_SSE, 0, 0, 0, 2, {0x0F, 0xE7, 0}, 0, 2,
-      {OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
+      {OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_64|OPA_Spare, 0} }
 };
 static const x86_insn_info movss_insn[] = {
     { CPU_SSE, 0, 0, 0, 3, {0xF3, 0x0F, 0x10}, 0, 2,
       {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} },
     { CPU_SSE, 0, 0, 0, 3, {0xF3, 0x0F, 0x10}, 0, 2,
-      {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+      {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_32|OPS_Relaxed|OPA_EA, 0} },
     { CPU_SSE, 0, 0, 0, 3, {0xF3, 0x0F, 0x11}, 0, 2,
-      {OPT_Mem|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
+      {OPT_Mem|OPS_32|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
 };
 static const x86_insn_info pextrw_insn[] = {
     { CPU_P3|CPU_MMX, 0, 0, 0, 2, {0x0F, 0xC5, 0}, 0, 3,
@@ -3339,12 +3339,12 @@ yasm_x86__parse_check_id(yasm_arch *arch, unsigned long data[4],
 	P A D D U S W { RET_INSN(mmxsse2, 0xDD, CPU_MMX); }
 	P A N D { RET_INSN(mmxsse2, 0xDB, CPU_MMX); }
 	P A N D N { RET_INSN(mmxsse2, 0xDF, CPU_MMX); }
-	P A C M P E Q B { RET_INSN(mmxsse2, 0x74, CPU_MMX); }
-	P A C M P E Q W { RET_INSN(mmxsse2, 0x75, CPU_MMX); }
-	P A C M P E Q D { RET_INSN(mmxsse2, 0x76, CPU_MMX); }
-	P A C M P G T B { RET_INSN(mmxsse2, 0x64, CPU_MMX); }
-	P A C M P G T W { RET_INSN(mmxsse2, 0x65, CPU_MMX); }
-	P A C M P G T D { RET_INSN(mmxsse2, 0x66, CPU_MMX); }
+	P C M P E Q B { RET_INSN(mmxsse2, 0x74, CPU_MMX); }
+	P C M P E Q W { RET_INSN(mmxsse2, 0x75, CPU_MMX); }
+	P C M P E Q D { RET_INSN(mmxsse2, 0x76, CPU_MMX); }
+	P C M P G T B { RET_INSN(mmxsse2, 0x64, CPU_MMX); }
+	P C M P G T W { RET_INSN(mmxsse2, 0x65, CPU_MMX); }
+	P C M P G T D { RET_INSN(mmxsse2, 0x66, CPU_MMX); }
 	P M A D D W D { RET_INSN(mmxsse2, 0xF5, CPU_MMX); }
 	P M U L H W { RET_INSN(mmxsse2, 0xE5, CPU_MMX); }
 	P M U L L W { RET_INSN(mmxsse2, 0xD5, CPU_MMX); }