From: Eric Christopher Date: Fri, 14 Jun 2019 04:51:55 +0000 (+0000) Subject: Move commentary on opcode translation for code16 mov instructions X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=7a01be2925f2e75b217b0b8ac744a96415b92fcd;p=llvm Move commentary on opcode translation for code16 mov instructions to segment registers closer to the segment register check for when we add further optimizations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363355 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp index 8387b9549c1..95cbf46d37e 100644 --- a/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -2678,13 +2678,13 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, static_cast(*Operands[0]).setTokenValue(Repl); } - // Moving a 32 or 16 bit value into a segment register has the same - // behavior. Modify such instructions to always take shorter form. if ((Name == "mov" || Name == "movw" || Name == "movl") && (Operands.size() == 3)) { X86Operand &Op1 = (X86Operand &)*Operands[1]; X86Operand &Op2 = (X86Operand &)*Operands[2]; SMLoc Loc = Op1.getEndLoc(); + // Moving a 32 or 16 bit value into a segment register has the same + // behavior. Modify such instructions to always take shorter form. if (Op1.isReg() && Op2.isReg() && X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains( Op2.getReg()) &&