From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Sun, 20 Jan 2019 19:28:20 +0000 (+0000)
Subject: AMDGPU/GlobalISel: Really legalize exts from i1
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=761822022147a59d7bda644635c742e7eab0c0bc;p=llvm

AMDGPU/GlobalISel: Really legalize exts from i1

There is a combine that was hiding these tests
not actually testing what they should be, although
they were producing the expected end result.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351698 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 200840e93b2..2beed6e8903 100644
--- a/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -158,7 +158,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
   setAction({G_FCMP, 1, S64}, Legal);
 
   getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
-    .legalFor({{S64, S32}, {S32, S16}, {S64, S16}});
+    .legalFor({{S64, S32}, {S32, S16}, {S64, S16},
+               {S32, S1}, {S64, S1}, {S16, S1}});
 
   setAction({G_FPTOSI, S32}, Legal);
   setAction({G_FPTOSI, 1, S32}, Legal);
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
index 73f150028c2..b567cadaaf5 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
@@ -49,17 +49,29 @@ body: |
 ...
 
 ---
-name: test_anyext_i1_to_s32
+name: test_anyext_s1_to_s32
 body: |
   bb.0.entry:
-    liveins: $vgpr0
 
-    ; CHECK-LABEL: name: test_anyext_i1_to_s32
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
-    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
-    %0:_(s32) = COPY $vgpr0
-    %1:_(s1) = G_TRUNC %0
-    %2:_(s32) = G_ANYEXT %1
-    $vgpr0 = COPY %2
+    ; CHECK-LABEL: name: test_anyext_s1_to_s32
+    ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s1)
+    ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
+    %0:_(s1) = G_CONSTANT i1 0
+    %1:_(s32) = G_ANYEXT %0
+    $vgpr0 = COPY %1
+...
+
+---
+name: test_anyext_s1_to_s64
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: name: test_anyext_s1_to_s64
+    ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s1)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
+    %0:_(s1) = G_CONSTANT i1 0
+    %1:_(s64) = G_ANYEXT %0
+    $vgpr0_vgpr1 = COPY %1
 ...
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
index 1761681546f..5794cb52f64 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
@@ -56,16 +56,26 @@ body: |
 name: test_zext_i1_to_s32
 body: |
   bb.0.entry:
-    liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_zext_i1_to_s32
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
-    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
-    ; CHECK: $vgpr0 = COPY [[AND]](s32)
-    %0:_(s32) = COPY $vgpr0
-    %1:_(s1) = G_TRUNC %0
-    %2:_(s32) = G_ZEXT %1
-    $vgpr0 = COPY %2
+    ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[C]](s1)
+    ; CHECK: $vgpr0 = COPY [[ZEXT]](s32)
+    %0:_(s1) = G_CONSTANT i1 0
+    %1:_(s32) = G_ZEXT %0
+    $vgpr0 = COPY %1
+...
+
+---
+name: test_zext_i1_to_i64
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: name: test_zext_i1_to_i64
+    ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s1)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+    %0:_(s1) = G_CONSTANT i1 0
+    %1:_(s64) = G_ZEXT %0
+    $vgpr0_vgpr1 = COPY %1
 ...