From: Javed Absar Date: Sun, 27 Aug 2017 14:46:57 +0000 (+0000) Subject: [ARM] Tidy-up ARMAsmParser. NFC. X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=75f84acf16b26d06d24327c9cc6d50c84421d4e3;p=llvm [ARM] Tidy-up ARMAsmParser. NFC. Simplify getDRegFromQReg function Reviewed by: @fhahn, @asb Differential Revision: https://reviews.llvm.org/D37118 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311850 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 1246cf3bb58..ebe6dac3a4c 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -264,6 +264,11 @@ class ARMAsmParser : public MCTargetAsmParser { return; } + // Return the low-subreg of a given Q register. + unsigned getDRegFromQReg(unsigned QReg) const { + return MRI->getSubReg(QReg, ARM::dsub_0); + } + // Get the encoding of the IT mask, as it will appear in an IT instruction. unsigned getITMaskEncoding() { assert(inITBlock()); @@ -3462,29 +3467,6 @@ static unsigned getNextRegister(unsigned Reg) { } } -// Return the low-subreg of a given Q register. -static unsigned getDRegFromQReg(unsigned QReg) { - switch (QReg) { - default: llvm_unreachable("expected a Q register!"); - case ARM::Q0: return ARM::D0; - case ARM::Q1: return ARM::D2; - case ARM::Q2: return ARM::D4; - case ARM::Q3: return ARM::D6; - case ARM::Q4: return ARM::D8; - case ARM::Q5: return ARM::D10; - case ARM::Q6: return ARM::D12; - case ARM::Q7: return ARM::D14; - case ARM::Q8: return ARM::D16; - case ARM::Q9: return ARM::D18; - case ARM::Q10: return ARM::D20; - case ARM::Q11: return ARM::D22; - case ARM::Q12: return ARM::D24; - case ARM::Q13: return ARM::D26; - case ARM::Q14: return ARM::D28; - case ARM::Q15: return ARM::D30; - } -} - /// Parse a register list. bool ARMAsmParser::parseRegisterList(OperandVector &Operands) { MCAsmParser &Parser = getParser();