From: Craig Topper <craig.topper@intel.com>
Date: Sun, 26 Nov 2017 21:14:48 +0000 (+0000)
Subject: [X86] Fix an assert that was incorrectly checking for BMI instead of AVX512VBMI.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=75de121e01e390e4ca6e7e51c10ad27006cdc97a;p=llvm

[X86] Fix an assert that was incorrectly checking for BMI instead of AVX512VBMI.

The check is actually unnecessary since AVX512VBMI implies AVX512BW which is the other part of the assert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319006 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 892c7e24abd..5f4e4d7a113 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -2149,8 +2149,7 @@ static void Passv64i1ArgInRegs(
     const SDLoc &Dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg,
     SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, CCValAssign &VA,
     CCValAssign &NextVA, const X86Subtarget &Subtarget) {
-  assert((Subtarget.hasBWI() || Subtarget.hasBMI()) &&
-         "Expected AVX512BW or AVX512BMI target!");
+  assert(Subtarget.hasBWI() && "Expected AVX512BW target!");
   assert(Subtarget.is32Bit() && "Expecting 32 bit target");
   assert(Arg.getValueType() == MVT::i64 && "Expecting 64 bit value");
   assert(VA.isRegLoc() && NextVA.isRegLoc() &&