From: Craig Topper Date: Tue, 10 May 2016 05:27:56 +0000 (+0000) Subject: [X86] Update X86_INTR calling convention to save ZMM registers instead of YMM registe... X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=7522f0e895ac74c36df46b31ee932496f5434107;p=llvm [X86] Update X86_INTR calling convention to save ZMM registers instead of YMM registers when AVX512 is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269017 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/X86CallingConv.td b/lib/Target/X86/X86CallingConv.td index b8c473dcbac..a34d90185ca 100644 --- a/lib/Target/X86/X86CallingConv.td +++ b/lib/Target/X86/X86CallingConv.td @@ -899,8 +899,9 @@ def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX, RSP, def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, RSP, (sequence "YMM%u", 0, 15)), (sequence "XMM%u", 0, 15))>; -def CSR_64_AllRegs_AVX512 : CalleeSavedRegs<(add CSR_64_AllRegs_AVX, - (sequence "YMM%u", 16, 31))>; +def CSR_64_AllRegs_AVX512 : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, RSP, + (sequence "ZMM%u", 0, 31)), + (sequence "XMM%u", 0, 15))>; // Standard C + YMM6-15 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, diff --git a/test/CodeGen/X86/x86-interrupt_cc.ll b/test/CodeGen/X86/x86-interrupt_cc.ll index f5d2b39fc63..8c5dfb1d5d0 100644 --- a/test/CodeGen/X86/x86-interrupt_cc.ll +++ b/test/CodeGen/X86/x86-interrupt_cc.ll @@ -3,10 +3,10 @@ ; Make sure we spill the high numbered YMM registers with the right encoding. ; CHECK-LABEL: foo -; CHECK: movups %ymm31, {{.+}} -; CHECK: encoding: [0x62,0x61,0x7c,0x28,0x11,0xbc,0x24,0xf0,0x03,0x00,0x00] -; ymm30 is used as an anchor for the previous regexp. -; CHECK-NEXT: movups %ymm30 +; CHECK: movups %zmm31, {{.+}} +; CHECK: encoding: [0x62,0x61,0x7c,0x48,0x11,0xbc,0x24,0x10,0x08,0x00,0x00] +; zmm30 is used as an anchor for the previous regexp. +; CHECK-NEXT: movups %zmm30 ; CHECK: call ; CHECK: iret