From: Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net>
Date: Wed, 18 Jul 2018 11:16:31 +0000 (+0000)
Subject: [TargetInstPredicate] Add definition of CheckInvalidRegisterOperand.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=73ce7fc085cc55fc61a4c5f2ecf352814c7a6162;p=llvm

[TargetInstPredicate] Add definition of CheckInvalidRegisterOperand.

This should have been part of r337378. I forgot to svn add it before committing
the change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337380 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/llvm/Target/TargetInstrPredicate.td b/include/llvm/Target/TargetInstrPredicate.td
index e6e5c06cd03..d38279b0d65 100644
--- a/include/llvm/Target/TargetInstrPredicate.td
+++ b/include/llvm/Target/TargetInstrPredicate.td
@@ -111,6 +111,9 @@ class CheckRegOperand<int Index, Register R> : MCOperandPredicate<Index> {
   Register Reg = R;
 }
 
+// Check if register operand at index `Index` is the invalid register.
+class CheckInvalidRegOperand<int Index> : MCOperandPredicate<Index>;
+
 // Check that the operand at position `Index` is immediate `Imm`.
 class CheckImmOperand<int Index, int Imm> : MCOperandPredicate<Index> {
   int ImmVal = Imm;