From: Valery Pykhtin <Valery.Pykhtin@amd.com>
Date: Thu, 7 Jul 2016 14:23:38 +0000 (+0000)
Subject: [AMDGPU] fix ds_write_src2 encoding (bz26027)
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=73a50c1cbffadf4cbcb7870560d4f6880ecf256e;p=llvm

[AMDGPU] fix ds_write_src2 encoding (bz26027)

Differential revision: http://reviews.llvm.org/D22041

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274756 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/SIInstrInfo.td b/lib/Target/AMDGPU/SIInstrInfo.td
index 708d97e9773..339cfd4dfdf 100644
--- a/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/lib/Target/AMDGPU/SIInstrInfo.td
@@ -2632,6 +2632,20 @@ multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc,
   }
 }
 
+multiclass DS_1A_Off8_NORET <bits<8> op, string opName,
+  dag outs = (outs),
+  dag ins = (ins VGPR_32:$addr,
+              offset0:$offset0, offset1:$offset1, gds:$gds),
+  string asm = opName#" $addr $offset0"#"$offset1$gds"> {
+
+  def "" : DS_Pseudo <opName, outs, ins, []>;
+
+  let data0 = 0, data1 = 0, vdst = 0, AsmMatchConverter = "cvtDSOffset01" in {
+    def _si : DS_Real_si <op, opName, outs, ins, asm>;
+    def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
+  }
+}
+
 multiclass DS_1A2D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
   dag outs = (outs),
   dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
diff --git a/lib/Target/AMDGPU/SIInstructions.td b/lib/Target/AMDGPU/SIInstructions.td
index ce69b410d40..9eff2e056a8 100644
--- a/lib/Target/AMDGPU/SIInstructions.td
+++ b/lib/Target/AMDGPU/SIInstructions.td
@@ -902,7 +902,7 @@ defm DS_MAX_SRC2_U32 : DS_1A <0x88, "ds_max_src2_u32">;
 defm DS_AND_SRC2_B32 : DS_1A <0x89, "ds_and_src_b32">;
 defm DS_OR_SRC2_B32 : DS_1A <0x8a, "ds_or_src2_b32">;
 defm DS_XOR_SRC2_B32 : DS_1A <0x8b, "ds_xor_src2_b32">;
-defm DS_WRITE_SRC2_B32 : DS_1A <0x8c, "ds_write_src2_b32">;
+defm DS_WRITE_SRC2_B32 : DS_1A_Off8_NORET <0x8d, "ds_write_src2_b32">;
 
 defm DS_MIN_SRC2_F32 : DS_1A <0x92, "ds_min_src2_f32">;
 defm DS_MAX_SRC2_F32 : DS_1A <0x93, "ds_max_src2_f32">;
@@ -919,7 +919,7 @@ defm DS_MAX_SRC2_U64 : DS_1A <0xc8, "ds_max_src2_u64">;
 defm DS_AND_SRC2_B64 : DS_1A <0xc9, "ds_and_src2_b64">;
 defm DS_OR_SRC2_B64 : DS_1A <0xca, "ds_or_src2_b64">;
 defm DS_XOR_SRC2_B64 : DS_1A <0xcb, "ds_xor_src2_b64">;
-defm DS_WRITE_SRC2_B64 : DS_1A <0xcc, "ds_write_src2_b64">;
+defm DS_WRITE_SRC2_B64 : DS_1A_Off8_NORET <0xcd, "ds_write_src2_b64">;
 
 defm DS_MIN_SRC2_F64 : DS_1A <0xd2, "ds_min_src2_f64">;
 defm DS_MAX_SRC2_F64 : DS_1A <0xd3, "ds_max_src2_f64">;
diff --git a/test/MC/AMDGPU/ds.s b/test/MC/AMDGPU/ds.s
index 224def8a84c..c0fd05cece0 100644
--- a/test/MC/AMDGPU/ds.s
+++ b/test/MC/AMDGPU/ds.s
@@ -14,6 +14,14 @@ ds_add_u32 v2, v4 offset:16
 // Checks for 2 8-bit Offsets
 //===----------------------------------------------------------------------===//
 
+ds_write_src2_b32 v2 offset0:4 offset1:8
+// SICI: ds_write_src2_b32 v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x34,0xda,0x02,0x00,0x00,0x00]
+// VI:   ds_write_src2_b32 v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x1a,0xd9,0x02,0x00,0x00,0x00]
+
+ds_write_src2_b64 v2 offset0:4 offset1:8
+// SICI: ds_write_src2_b64 v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x34,0xdb,0x02,0x00,0x00,0x00]
+// VI:   ds_write_src2_b64 v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x9a,0xd9,0x02,0x00,0x00,0x00]
+
 ds_write2_b32 v2, v4, v6 offset0:4
 // SICI: ds_write2_b32 v2, v4, v6 offset0:4 ; encoding: [0x04,0x00,0x38,0xd8,0x02,0x04,0x06,0x00]
 // VI:   ds_write2_b32 v2, v4, v6 offset0:4 ; encoding: [0x04,0x00,0x1c,0xd8,0x02,0x04,0x06,0x00]