From: Sander de Smalen Date: Tue, 17 Jul 2018 13:58:46 +0000 (+0000) Subject: [AArch64][SVE] Asm: FP fused multiply-add/subtract instructions. X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=73739643d7bc75aacfd5455b37b31376ad20af25;p=llvm [AArch64][SVE] Asm: FP fused multiply-add/subtract instructions. This patch adds support for the following instructions: FMLA mul-add, writing addend (Zda = Zda + Zn * Zm) FNMLA negated mul-add, writing addend (Zda = -Zda + -Zn * Zm) FMLS mul-sub, writing addend (Zda = Zda + -Zn * Zm) FNMLS negated mul-sub, writing addend (Zda = -Zda + Zn * Zm) FMAD mul-add, writing multiplicant (Zdn = Za + Zdn * Zm) FNMAD negated mul-add, writing multiplicant (Zdn = -Za + -Zdn * Zm) FMSB mul-sub, writing multiplicant (Zdn = Za + -Zdn * Zm) FNMSB negated mul-sub, writing multiplicant (Zdn = -Za + Zdn * Zm) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337282 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/AArch64/AArch64SVEInstrInfo.td b/lib/Target/AArch64/AArch64SVEInstrInfo.td index b9de1f61fe7..60114f7f479 100644 --- a/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -107,6 +107,19 @@ let Predicates = [HasSVE] in { defm FCADD_ZPmZ : sve_fp_fcadd<"fcadd">; defm FCMLA_ZPmZZ : sve_fp_fcmla<"fcmla">; + defm FMLA_ZPmZZ : sve_fp_3op_p_zds_a<0b00, "fmla">; + defm FMLS_ZPmZZ : sve_fp_3op_p_zds_a<0b01, "fmls">; + defm FNMLA_ZPmZZ : sve_fp_3op_p_zds_a<0b10, "fnmla">; + defm FNMLS_ZPmZZ : sve_fp_3op_p_zds_a<0b11, "fnmls">; + + defm FMAD_ZPmZZ : sve_fp_3op_p_zds_b<0b00, "fmad">; + defm FMSB_ZPmZZ : sve_fp_3op_p_zds_b<0b01, "fmsb">; + defm FNMAD_ZPmZZ : sve_fp_3op_p_zds_b<0b10, "fnmad">; + defm FNMSB_ZPmZZ : sve_fp_3op_p_zds_b<0b11, "fnmsb">; + + defm FMLA_ZZZI : sve_fp_fma_by_indexed_elem<0b0, "fmla">; + defm FMLS_ZZZI : sve_fp_fma_by_indexed_elem<0b1, "fmls">; + defm FCMLA_ZZZI : sve_fp_fcmla_by_indexed_elem<"fcmla">; defm FMUL_ZZZI : sve_fp_fmul_by_indexed_elem<"fmul">; diff --git a/lib/Target/AArch64/SVEInstrFormats.td b/lib/Target/AArch64/SVEInstrFormats.td index 5be8ef1afd2..39397447fea 100644 --- a/lib/Target/AArch64/SVEInstrFormats.td +++ b/lib/Target/AArch64/SVEInstrFormats.td @@ -986,6 +986,112 @@ multiclass sve_fp_2op_p_zds opc, string asm> { } +//===----------------------------------------------------------------------===// +// SVE Floating Point Fused Multiply-Add Group +//===----------------------------------------------------------------------===// + +class sve_fp_3op_p_zds_a sz, bits<2> opc, string asm, ZPRRegOp zprty> +: I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm), + asm, "\t$Zda, $Pg/m, $Zn, $Zm", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Zda; + bits<5> Zm; + bits<5> Zn; + let Inst{31-24} = 0b01100101; + let Inst{23-22} = sz; + let Inst{21} = 0b1; + let Inst{20-16} = Zm; + let Inst{15} = 0b0; + let Inst{14-13} = opc; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4-0} = Zda; + + let Constraints = "$Zda = $_Zda"; +} + +multiclass sve_fp_3op_p_zds_a opc, string asm> { + def _H : sve_fp_3op_p_zds_a<0b01, opc, asm, ZPR16>; + def _S : sve_fp_3op_p_zds_a<0b10, opc, asm, ZPR32>; + def _D : sve_fp_3op_p_zds_a<0b11, opc, asm, ZPR64>; +} + +class sve_fp_3op_p_zds_b sz, bits<2> opc, string asm, + ZPRRegOp zprty> +: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za), + asm, "\t$Zdn, $Pg/m, $Zm, $Za", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Za; + bits<5> Zdn; + bits<5> Zm; + let Inst{31-24} = 0b01100101; + let Inst{23-22} = sz; + let Inst{21} = 0b1; + let Inst{20-16} = Za; + let Inst{15} = 0b1; + let Inst{14-13} = opc; + let Inst{12-10} = Pg; + let Inst{9-5} = Zm; + let Inst{4-0} = Zdn; + + let Constraints = "$Zdn = $_Zdn"; +} + +multiclass sve_fp_3op_p_zds_b opc, string asm> { + def _H : sve_fp_3op_p_zds_b<0b01, opc, asm, ZPR16>; + def _S : sve_fp_3op_p_zds_b<0b10, opc, asm, ZPR32>; + def _D : sve_fp_3op_p_zds_b<0b11, opc, asm, ZPR64>; +} + +//===----------------------------------------------------------------------===// +// SVE Floating Point Multiply-Add - Indexed Group +//===----------------------------------------------------------------------===// + +class sve_fp_fma_by_indexed_elem sz, bit opc, string asm, + ZPRRegOp zprty1, + ZPRRegOp zprty2, Operand itype> +: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty1:$Zn, zprty2:$Zm, itype:$iop), + asm, "\t$Zda, $Zn, $Zm$iop", "", []>, Sched<[]> { + bits<5> Zda; + bits<5> Zn; + let Inst{31-24} = 0b01100100; + let Inst{23-22} = sz; + let Inst{21} = 0b1; + let Inst{15-11} = 0; + let Inst{10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zda; + + let Constraints = "$Zda = $_Zda"; +} + +multiclass sve_fp_fma_by_indexed_elem { + def _H : sve_fp_fma_by_indexed_elem<{0, ?}, opc, asm, ZPR16, ZPR3b16, VectorIndexH> { + bits<3> Zm; + bits<3> iop; + let Inst{22} = iop{2}; + let Inst{20-19} = iop{1-0}; + let Inst{18-16} = Zm; + } + def _S : sve_fp_fma_by_indexed_elem<0b10, opc, asm, ZPR32, ZPR3b32, VectorIndexS> { + bits<3> Zm; + bits<2> iop; + let Inst{20-19} = iop; + let Inst{18-16} = Zm; + } + def _D : sve_fp_fma_by_indexed_elem<0b11, opc, asm, ZPR64, ZPR4b64, VectorIndexD> { + bits<4> Zm; + bit iop; + let Inst{20} = iop; + let Inst{19-16} = Zm; + } +} + + //===----------------------------------------------------------------------===// // SVE Floating Point Multiply - Indexed Group //===----------------------------------------------------------------------===// diff --git a/test/MC/AArch64/SVE/fmad-diagnostics.s b/test/MC/AArch64/SVE/fmad-diagnostics.s new file mode 100644 index 00000000000..ab9301c97c5 --- /dev/null +++ b/test/MC/AArch64/SVE/fmad-diagnostics.s @@ -0,0 +1,33 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid predicate + +fmad z0.h, p8/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fmad z0.h, p8/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element width + +fmad z0.s, p7/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmad z0.s, p7/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmad z0.b, p7/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmad z0.b, p7/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Element index is not allowed + +fmad z0.h, p7/m, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: fmad z0.h, p7/m, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fmad.s b/test/MC/AArch64/SVE/fmad.s new file mode 100644 index 00000000000..dbcec437c32 --- /dev/null +++ b/test/MC/AArch64/SVE/fmad.s @@ -0,0 +1,26 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +fmad z0.h, p7/m, z1.h, z31.h +// CHECK-INST: fmad z0.h, p7/m, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x9c,0x7f,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 9c 7f 65 + +fmad z0.s, p7/m, z1.s, z31.s +// CHECK-INST: fmad z0.s, p7/m, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x9c,0xbf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 9c bf 65 + +fmad z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fmad z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x9c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 9c ff 65 diff --git a/test/MC/AArch64/SVE/fmla-diagnostics.s b/test/MC/AArch64/SVE/fmla-diagnostics.s new file mode 100644 index 00000000000..43b452f1e7b --- /dev/null +++ b/test/MC/AArch64/SVE/fmla-diagnostics.s @@ -0,0 +1,72 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid predicate + +fmla z0.h, p8/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fmla z0.h, p8/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element width + +fmla z0.s, p7/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmla z0.s, p7/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +fmla z0.h, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h +// CHECK-NEXT: fmla z0.h, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmla z0.s, z1.s, z8.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.s..z7.s +// CHECK-NEXT: fmla z0.s, z1.s, z8.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmla z0.d, z1.d, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d +// CHECK-NEXT: fmla z0.d, z1.d, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element index + +fmla z0.h, z1.h, z2.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: fmla z0.h, z1.h, z2.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmla z0.h, z1.h, z2.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: fmla z0.h, z1.h, z2.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmla z0.s, z1.s, z2.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: fmla z0.s, z1.s, z2.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmla z0.s, z1.s, z2.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: fmla z0.s, z1.s, z2.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmla z0.d, z1.d, z2.d[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: fmla z0.d, z1.d, z2.d[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmla z0.d, z1.d, z2.d[2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: fmla z0.d, z1.d, z2.d[2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fmla.s b/test/MC/AArch64/SVE/fmla.s new file mode 100644 index 00000000000..3b1f54c3759 --- /dev/null +++ b/test/MC/AArch64/SVE/fmla.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +fmla z0.h, p7/m, z1.h, z31.h +// CHECK-INST: fmla z0.h, p7/m, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x1c,0x7f,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 1c 7f 65 + +fmla z0.s, p7/m, z1.s, z31.s +// CHECK-INST: fmla z0.s, p7/m, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x1c,0xbf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 1c bf 65 + +fmla z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fmla z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x1c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 1c ff 65 + +fmla z0.h, z1.h, z7.h[7] +// CHECK-INST: fmla z0.h, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0x00,0x7f,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 00 7f 64 + +fmla z0.s, z1.s, z7.s[3] +// CHECK-INST: fmla z0.s, z1.s, z7.s[3] +// CHECK-ENCODING: [0x20,0x00,0xbf,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 00 bf 64 + +fmla z0.d, z1.d, z7.d[1] +// CHECK-INST: fmla z0.d, z1.d, z7.d[1] +// CHECK-ENCODING: [0x20,0x00,0xf7,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 00 f7 64 diff --git a/test/MC/AArch64/SVE/fmls-diagnostics.s b/test/MC/AArch64/SVE/fmls-diagnostics.s new file mode 100644 index 00000000000..f7734f8fe9a --- /dev/null +++ b/test/MC/AArch64/SVE/fmls-diagnostics.s @@ -0,0 +1,72 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid predicate + +fmls z0.h, p8/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fmls z0.h, p8/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element width + +fmls z0.s, p7/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmls z0.s, p7/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +fmls z0.h, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h +// CHECK-NEXT: fmls z0.h, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmls z0.s, z1.s, z8.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.s..z7.s +// CHECK-NEXT: fmls z0.s, z1.s, z8.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmls z0.d, z1.d, z16.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d +// CHECK-NEXT: fmls z0.d, z1.d, z16.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element index + +fmls z0.h, z1.h, z2.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: fmls z0.h, z1.h, z2.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmls z0.h, z1.h, z2.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: fmls z0.h, z1.h, z2.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmls z0.s, z1.s, z2.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: fmls z0.s, z1.s, z2.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmls z0.s, z1.s, z2.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: fmls z0.s, z1.s, z2.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmls z0.d, z1.d, z2.d[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: fmls z0.d, z1.d, z2.d[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmls z0.d, z1.d, z2.d[2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: fmls z0.d, z1.d, z2.d[2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fmls.s b/test/MC/AArch64/SVE/fmls.s new file mode 100644 index 00000000000..c337d8c3aec --- /dev/null +++ b/test/MC/AArch64/SVE/fmls.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +fmls z0.h, p7/m, z1.h, z31.h +// CHECK-INST: fmls z0.h, p7/m, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x3c,0x7f,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 3c 7f 65 + +fmls z0.s, p7/m, z1.s, z31.s +// CHECK-INST: fmls z0.s, p7/m, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x3c,0xbf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 3c bf 65 + +fmls z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fmls z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x3c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 3c ff 65 + +fmls z0.h, z1.h, z7.h[7] +// CHECK-INST: fmls z0.h, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0x04,0x7f,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 04 7f 64 + +fmls z0.s, z1.s, z7.s[3] +// CHECK-INST: fmls z0.s, z1.s, z7.s[3] +// CHECK-ENCODING: [0x20,0x04,0xbf,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 04 bf 64 + +fmls z0.d, z1.d, z7.d[1] +// CHECK-INST: fmls z0.d, z1.d, z7.d[1] +// CHECK-ENCODING: [0x20,0x04,0xf7,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 04 f7 64 diff --git a/test/MC/AArch64/SVE/fmsb-diagnostics.s b/test/MC/AArch64/SVE/fmsb-diagnostics.s new file mode 100644 index 00000000000..df4dbe54fb1 --- /dev/null +++ b/test/MC/AArch64/SVE/fmsb-diagnostics.s @@ -0,0 +1,33 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid predicate + +fmsb z0.h, p8/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fmsb z0.h, p8/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element width + +fmsb z0.s, p7/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmsb z0.s, p7/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmsb z0.b, p7/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmsb z0.b, p7/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Element index is not allowed + +fmsb z0.h, p7/m, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: fmsb z0.h, p7/m, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fmsb.s b/test/MC/AArch64/SVE/fmsb.s new file mode 100644 index 00000000000..4e34073ff10 --- /dev/null +++ b/test/MC/AArch64/SVE/fmsb.s @@ -0,0 +1,26 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +fmsb z0.h, p7/m, z1.h, z31.h +// CHECK-INST: fmsb z0.h, p7/m, z1.h, z31.h +// CHECK-ENCODING: [0x20,0xbc,0x7f,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 bc 7f 65 + +fmsb z0.s, p7/m, z1.s, z31.s +// CHECK-INST: fmsb z0.s, p7/m, z1.s, z31.s +// CHECK-ENCODING: [0x20,0xbc,0xbf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 bc bf 65 + +fmsb z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fmsb z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xbc,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 bc ff 65 diff --git a/test/MC/AArch64/SVE/fnmad-diagnostics.s b/test/MC/AArch64/SVE/fnmad-diagnostics.s new file mode 100644 index 00000000000..8d12d89d631 --- /dev/null +++ b/test/MC/AArch64/SVE/fnmad-diagnostics.s @@ -0,0 +1,33 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid predicate + +fnmad z0.h, p8/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fnmad z0.h, p8/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element width + +fnmad z0.s, p7/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fnmad z0.s, p7/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fnmad z0.b, p7/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fnmad z0.b, p7/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Element index is not allowed + +fnmad z0.h, p7/m, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: fnmad z0.h, p7/m, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fnmad.s b/test/MC/AArch64/SVE/fnmad.s new file mode 100644 index 00000000000..6bb736c9eb4 --- /dev/null +++ b/test/MC/AArch64/SVE/fnmad.s @@ -0,0 +1,26 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +fnmad z0.h, p7/m, z1.h, z31.h +// CHECK-INST: fnmad z0.h, p7/m, z1.h, z31.h +// CHECK-ENCODING: [0x20,0xdc,0x7f,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 dc 7f 65 + +fnmad z0.s, p7/m, z1.s, z31.s +// CHECK-INST: fnmad z0.s, p7/m, z1.s, z31.s +// CHECK-ENCODING: [0x20,0xdc,0xbf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 dc bf 65 + +fnmad z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fnmad z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xdc,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 dc ff 65 diff --git a/test/MC/AArch64/SVE/fnmla-diagnostics.s b/test/MC/AArch64/SVE/fnmla-diagnostics.s new file mode 100644 index 00000000000..df9053c4b9d --- /dev/null +++ b/test/MC/AArch64/SVE/fnmla-diagnostics.s @@ -0,0 +1,28 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid predicate + +fnmla z0.h, p8/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fnmla z0.h, p8/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element width + +fnmla z0.s, p7/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fnmla z0.s, p7/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Element index is not allowed + +fnmla z0.h, p7/m, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: fnmla z0.h, p7/m, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fnmla.s b/test/MC/AArch64/SVE/fnmla.s new file mode 100644 index 00000000000..49d443f2610 --- /dev/null +++ b/test/MC/AArch64/SVE/fnmla.s @@ -0,0 +1,26 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +fnmla z0.h, p7/m, z1.h, z31.h +// CHECK-INST: fnmla z0.h, p7/m, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x5c,0x7f,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 5c 7f 65 + +fnmla z0.s, p7/m, z1.s, z31.s +// CHECK-INST: fnmla z0.s, p7/m, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x5c,0xbf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 5c bf 65 + +fnmla z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fnmla z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x5c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 5c ff 65 diff --git a/test/MC/AArch64/SVE/fnmls-diagnostics.s b/test/MC/AArch64/SVE/fnmls-diagnostics.s new file mode 100644 index 00000000000..4136cb0f50e --- /dev/null +++ b/test/MC/AArch64/SVE/fnmls-diagnostics.s @@ -0,0 +1,28 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid predicate + +fnmls z0.h, p8/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fnmls z0.h, p8/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element width + +fnmls z0.s, p7/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fnmls z0.s, p7/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Element index is not allowed + +fnmls z0.h, p7/m, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: fnmls z0.h, p7/m, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fnmls.s b/test/MC/AArch64/SVE/fnmls.s new file mode 100644 index 00000000000..438fbaeed6d --- /dev/null +++ b/test/MC/AArch64/SVE/fnmls.s @@ -0,0 +1,26 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +fnmls z0.h, p7/m, z1.h, z31.h +// CHECK-INST: fnmls z0.h, p7/m, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x7c,0x7f,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 7c 7f 65 + +fnmls z0.s, p7/m, z1.s, z31.s +// CHECK-INST: fnmls z0.s, p7/m, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x7c,0xbf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 7c bf 65 + +fnmls z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fnmls z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x7c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 7c ff 65 diff --git a/test/MC/AArch64/SVE/fnmsb-diagnostics.s b/test/MC/AArch64/SVE/fnmsb-diagnostics.s new file mode 100644 index 00000000000..51981dda9a4 --- /dev/null +++ b/test/MC/AArch64/SVE/fnmsb-diagnostics.s @@ -0,0 +1,33 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid predicate + +fnmsb z0.h, p8/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fnmsb z0.h, p8/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element width + +fnmsb z0.s, p7/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fnmsb z0.s, p7/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fnmsb z0.b, p7/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fnmsb z0.b, p7/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Element index is not allowed + +fnmsb z0.h, p7/m, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: fnmsb z0.h, p7/m, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fnmsb.s b/test/MC/AArch64/SVE/fnmsb.s new file mode 100644 index 00000000000..f06de48afbf --- /dev/null +++ b/test/MC/AArch64/SVE/fnmsb.s @@ -0,0 +1,26 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +fnmsb z0.h, p7/m, z1.h, z31.h +// CHECK-INST: fnmsb z0.h, p7/m, z1.h, z31.h +// CHECK-ENCODING: [0x20,0xfc,0x7f,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 fc 7f 65 + +fnmsb z0.s, p7/m, z1.s, z31.s +// CHECK-INST: fnmsb z0.s, p7/m, z1.s, z31.s +// CHECK-ENCODING: [0x20,0xfc,0xbf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 fc bf 65 + +fnmsb z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fnmsb z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xfc,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 fc ff 65