From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Wed, 6 Dec 2017 11:59:05 +0000 (+0000)
Subject: [X86][AVX512] Tag Mask<->Vector instructions scheduler classes
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=735383658c691b9ee120793f9709aab45a5d5e11;p=llvm

[X86][AVX512] Tag Mask<->Vector instructions scheduler classes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319887 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td
index 3c4b00bd9f0..867b35d93ec 100644
--- a/lib/Target/X86/X86InstrAVX512.td
+++ b/lib/Target/X86/X86InstrAVX512.td
@@ -8676,7 +8676,8 @@ defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd
 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
                   !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
-                  [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
+                  [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))],
+                  IIC_SSE_MOV_S_RR>, EVEX, Sched<[WriteMove]>;
 }
 
 // Use 512bit version to implement 128/256 bit in case NoVLX.
@@ -8714,7 +8715,8 @@ defm VPMOVM2Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, "vpmovm2", HasDQI
 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
     def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
                         !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
-                        [(set _.KRC:$dst, (X86cvt2mask (_.VT _.RC:$src)))]>, EVEX;
+                        [(set _.KRC:$dst, (X86cvt2mask (_.VT _.RC:$src)))],
+                        IIC_SSE_MOV_S_RR>, EVEX, Sched<[WriteMove]>;
 }
 
 // Use 512bit version to implement 128/256 bit in case NoVLX.