From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Tue, 22 Jan 2019 18:53:41 +0000 (+0000)
Subject: GlobalISel: Disallow vectors for G_CONSTANT/G_FCONSTANT
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=730b10c319a7e8d5b5f69156b66c2bbde37c61ad;p=llvm

GlobalISel: Disallow vectors for G_CONSTANT/G_FCONSTANT

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351853 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/llvm/Target/GenericOpcodes.td b/include/llvm/Target/GenericOpcodes.td
index 0903c482a0f..669a07b6511 100644
--- a/include/llvm/Target/GenericOpcodes.td
+++ b/include/llvm/Target/GenericOpcodes.td
@@ -92,12 +92,14 @@ def G_BITCAST : GenericInstruction {
   let hasSideEffects = 0;
 }
 
+// Only supports scalar result types
 def G_CONSTANT : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins unknown:$imm);
   let hasSideEffects = 0;
 }
 
+// Only supports scalar result types
 def G_FCONSTANT : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins unknown:$imm);
diff --git a/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index c964e98f578..6248a49317c 100644
--- a/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -243,10 +243,8 @@ MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
                                                     const ConstantInt &Val) {
   LLT Ty = Res.getLLTTy(*getMRI());
 
-  assert((Ty.isScalar() || Ty.isPointer()) && "invalid operand type");
-
   const ConstantInt *NewVal = &Val;
-  if (Ty.getSizeInBits() != Val.getBitWidth())
+  if (Ty.getScalarSizeInBits() != Val.getBitWidth())
     NewVal = ConstantInt::get(getMF().getFunction().getContext(),
                               Val.getValue().sextOrTrunc(Ty.getSizeInBits()));
 
@@ -266,7 +264,7 @@ MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
 
 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
                                                      const ConstantFP &Val) {
-  assert(Res.getLLTTy(*getMRI()).isScalar() && "invalid operand type");
+  assert(!Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
 
   auto MIB = buildInstr(TargetOpcode::G_FCONSTANT);
   Res.addDefToMIB(*getMRI(), MIB);
diff --git a/lib/CodeGen/MachineVerifier.cpp b/lib/CodeGen/MachineVerifier.cpp
index b7e0f575406..ad7825ba3eb 100644
--- a/lib/CodeGen/MachineVerifier.cpp
+++ b/lib/CodeGen/MachineVerifier.cpp
@@ -990,6 +990,16 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
   switch(MI->getOpcode()) {
   default:
     break;
+  case TargetOpcode::G_CONSTANT:
+  case TargetOpcode::G_FCONSTANT: {
+    if (MI->getNumOperands() < MCID.getNumOperands())
+      break;
+
+    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
+    if (DstTy.isVector())
+      report("Instruction cannot use a vector result type", MI);
+    break;
+  }
   case TargetOpcode::G_LOAD:
   case TargetOpcode::G_STORE:
     // Generic loads and stores must have a single MachineMemOperand
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
index 1422ed2a4c9..480309d2741 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
@@ -53,23 +53,23 @@ body: |
 name: test_select_v2s32
 body: |
   bb.0:
-    liveins: $vgpr0
+    liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
     ; CHECK-LABEL: name: test_select_v2s32
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
-    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
-    ; CHECK: [[C1:%[0-9]+]]:_(<2 x s32>) = G_CONSTANT i32 1
-    ; CHECK: [[C2:%[0-9]+]]:_(<2 x s32>) = G_CONSTANT i32 2
-    ; CHECK: [[SELECT:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
+    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr1_vgpr2
+    ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr3_vgpr4
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
+    ; CHECK: [[SELECT:%[0-9]+]]:_(<2 x s32>) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
     ; CHECK: $vgpr0_vgpr1 = COPY [[SELECT]](<2 x s32>)
-    %0:_(s32) = G_CONSTANT i32 0
-    %1:_(s32) = COPY $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %1:_(<2 x s32>) = COPY $vgpr1_vgpr2
+    %2:_(<2 x s32>) = COPY $vgpr3_vgpr4
+    %4:_(s32) = G_CONSTANT i32 0
 
-    %2:_(s1) = G_ICMP intpred(ne), %0, %1
-    %3:_(<2 x s32>) = G_CONSTANT i32 1
-    %4:_(<2 x s32>) = G_CONSTANT i32 2
-    %5:_(<2 x s32>) = G_SELECT %2, %3, %4
-    $vgpr0_vgpr1 = COPY %5
+    %5:_(s1) = G_ICMP intpred(ne), %0, %4
+    %6:_(<2 x s32>) = G_SELECT %5, %1, %2
+    $vgpr0_vgpr1 = COPY %6
 
 ...
 
@@ -160,22 +160,22 @@ body: |
 name: test_select_v2s16
 body: |
   bb.0:
-    liveins: $vgpr0
+    liveins: $vgpr0, $vgpr1, $vgpr2
     ; CHECK-LABEL: name: test_select_v2s16
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
     ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
-    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
-    ; CHECK: [[C1:%[0-9]+]]:_(<2 x s16>) = G_CONSTANT i32 1
-    ; CHECK: [[C2:%[0-9]+]]:_(<2 x s16>) = G_CONSTANT i32 2
-    ; CHECK: [[SELECT:%[0-9]+]]:_(<2 x s16>) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY2]](s32), [[C]]
+    ; CHECK: [[SELECT:%[0-9]+]]:_(<2 x s16>) = G_SELECT [[ICMP]](s1), [[COPY]], [[COPY1]]
     ; CHECK: $vgpr0 = COPY [[SELECT]](<2 x s16>)
-    %0:_(s32) = G_CONSTANT i32 0
-    %1:_(s32) = COPY $vgpr0
+    %0:_(<2 x s16>) = COPY $vgpr0
+    %1:_(<2 x s16>) = COPY $vgpr1
+    %2:_(s32) = COPY $vgpr2
+    %3:_(s32) = G_CONSTANT i32 0
 
-    %2:_(s1) = G_ICMP intpred(ne), %0, %1
-    %3:_(<2 x s16>) = G_CONSTANT i32 1
-    %4:_(<2 x s16>) = G_CONSTANT i32 2
-    %5:_(<2 x s16>) = G_SELECT %2, %3, %4
+    %4:_(s1) = G_ICMP intpred(ne), %2, %3
+    %5:_(<2 x s16>) = G_SELECT %4, %0, %1
     $vgpr0 = COPY %5
 
 ...
diff --git a/test/Verifier/test_g_constant.mir b/test/Verifier/test_g_constant.mir
new file mode 100644
index 00000000000..2fa8d03505c
--- /dev/null
+++ b/test/Verifier/test_g_constant.mir
@@ -0,0 +1,18 @@
+#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: global-isel, aarch64-registered-target
+
+---
+name:            test_constant
+legalized:       true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+body:             |
+  bb.0:
+    ; CHECK: Bad machine code: Instruction cannot use a vector result type
+    %0:_(<2 x s32>) = G_CONSTANT i32 0
+
+    ; CHECK: Bad machine code: Too few operands
+    %1:_(s32) = G_CONSTANT
+...
diff --git a/test/Verifier/test_g_fconstant.mir b/test/Verifier/test_g_fconstant.mir
new file mode 100644
index 00000000000..fecc47de5be
--- /dev/null
+++ b/test/Verifier/test_g_fconstant.mir
@@ -0,0 +1,15 @@
+#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: global-isel, aarch64-registered-target
+
+---
+name:            test_fconstant_vector
+legalized:       true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+body:             |
+  bb.0:
+    ; CHECK: Bad machine code: Instruction cannot use a vector result type
+    %0:_(<2 x s32>) = G_FCONSTANT float 0.0
+...