From: Gabor Buella Date: Fri, 25 May 2018 06:34:42 +0000 (+0000) Subject: [x86] invpcid intrinsic X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=724adfbac3f1a69ecdfcff72eb8d47104be72ab1;p=clang [x86] invpcid intrinsic An intrinsic for an old instruction, as described in the Intel SDM. Reviewers: craig.topper, rnk Reviewed By: craig.topper, rnk Differential Revision: https://reviews.llvm.org/D47142 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@333256 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/clang/Basic/BuiltinsX86.def b/include/clang/Basic/BuiltinsX86.def index fc47eb3818..88a45715ab 100644 --- a/include/clang/Basic/BuiltinsX86.def +++ b/include/clang/Basic/BuiltinsX86.def @@ -1867,6 +1867,9 @@ TARGET_BUILTIN(__builtin_ia32_movdir64b, "vv*vC*", "n", "movdir64b") // PTWRITE TARGET_BUILTIN(__builtin_ia32_ptwrite32, "vUi", "n", "ptwrite") +// INVPCID +TARGET_BUILTIN(__builtin_ia32_invpcid, "vUiv*", "nc", "invpcid") + // MSVC TARGET_HEADER_BUILTIN(_BitScanForward, "UcUNi*UNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_BitScanReverse, "UcUNi*UNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") diff --git a/include/clang/Driver/Options.td b/include/clang/Driver/Options.td index 5a2b784c92..8e9502a610 100644 --- a/include/clang/Driver/Options.td +++ b/include/clang/Driver/Options.td @@ -2685,6 +2685,8 @@ def mfsgsbase : Flag<["-"], "mfsgsbase">, Group; def mno_fsgsbase : Flag<["-"], "mno-fsgsbase">, Group; def mfxsr : Flag<["-"], "mfxsr">, Group; def mno_fxsr : Flag<["-"], "mno-fxsr">, Group; +def minvpcid : Flag<["-"], "minvpcid">, Group; +def mno_invpcid : Flag<["-"], "mno-invpcid">, Group; def mgfni : Flag<["-"], "mgfni">, Group; def mno_gfni : Flag<["-"], "mno-gfni">, Group; def mlwp : Flag<["-"], "mlwp">, Group; diff --git a/lib/Basic/Targets/X86.cpp b/lib/Basic/Targets/X86.cpp index 1f8de5b599..43fbdc0329 100644 --- a/lib/Basic/Targets/X86.cpp +++ b/lib/Basic/Targets/X86.cpp @@ -182,6 +182,7 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "bmi", true); setFeatureEnabledImpl(Features, "bmi2", true); setFeatureEnabledImpl(Features, "fma", true); + setFeatureEnabledImpl(Features, "invpcid", true); setFeatureEnabledImpl(Features, "movbe", true); LLVM_FALLTHROUGH; case CK_IvyBridge: @@ -811,6 +812,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector &Features, HasPCONFIG = true; } else if (Feature == "+ptwrite") { HasPTWRITE = true; + } else if (Feature == "+invpcid") { + HasINVPCID = true; } X86SSEEnum Level = llvm::StringSwitch(Feature) @@ -1173,6 +1176,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__PCONFIG__"); if (HasPTWRITE) Builder.defineMacro("__PTWRITE__"); + if (HasINVPCID) + Builder.defineMacro("__INVPCID__"); // Each case falls through to the previous one here. switch (SSELevel) { @@ -1293,6 +1298,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const { .Case("fsgsbase", true) .Case("fxsr", true) .Case("gfni", true) + .Case("invpcid", true) .Case("lwp", true) .Case("lzcnt", true) .Case("mmx", true) @@ -1370,6 +1376,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const { .Case("fsgsbase", HasFSGSBASE) .Case("fxsr", HasFXSR) .Case("gfni", HasGFNI) + .Case("invpcid", HasINVPCID) .Case("lwp", HasLWP) .Case("lzcnt", HasLZCNT) .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) diff --git a/lib/Basic/Targets/X86.h b/lib/Basic/Targets/X86.h index 2db115cd11..5b862face9 100644 --- a/lib/Basic/Targets/X86.h +++ b/lib/Basic/Targets/X86.h @@ -106,6 +106,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo { bool HasMOVDIRI = false; bool HasMOVDIR64B = false; bool HasPTWRITE = false; + bool HasINVPCID = false; protected: /// Enumeration of all of the X86 CPUs supported by Clang. diff --git a/lib/Headers/CMakeLists.txt b/lib/Headers/CMakeLists.txt index b34bc9b558..1930d8e225 100644 --- a/lib/Headers/CMakeLists.txt +++ b/lib/Headers/CMakeLists.txt @@ -58,6 +58,7 @@ set(files immintrin.h intrin.h inttypes.h + invpcidintrin.h iso646.h limits.h lwpintrin.h diff --git a/lib/Headers/cpuid.h b/lib/Headers/cpuid.h index ce7dfb6989..fce6af52dd 100644 --- a/lib/Headers/cpuid.h +++ b/lib/Headers/cpuid.h @@ -156,6 +156,7 @@ #define bit_SMEP 0x00000080 #define bit_BMI2 0x00000100 #define bit_ENH_MOVSB 0x00000200 +#define bit_INVPCID 0x00000400 #define bit_RTM 0x00000800 #define bit_MPX 0x00004000 #define bit_AVX512F 0x00010000 diff --git a/lib/Headers/immintrin.h b/lib/Headers/immintrin.h index 59c7322e5f..f57a95eb8d 100644 --- a/lib/Headers/immintrin.h +++ b/lib/Headers/immintrin.h @@ -376,4 +376,8 @@ _writegsbase_u64(unsigned long long __V) #include #endif +#if !defined(_MSC_VER) || __has_feature(modules) || defined(__INVPCID__) +#include +#endif + #endif /* __IMMINTRIN_H */ diff --git a/lib/Headers/invpcidintrin.h b/lib/Headers/invpcidintrin.h new file mode 100644 index 0000000000..c30a19fa3d --- /dev/null +++ b/lib/Headers/invpcidintrin.h @@ -0,0 +1,37 @@ +/*===------------- invpcidintrin.h - INVPCID intrinsic ---------------------=== + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + *===-----------------------------------------------------------------------=== + */ + +#ifndef __IMMINTRIN_H +#error "Never use directly; include instead." +#endif + +#ifndef __INVPCIDINTRIN_H +#define __INVPCIDINTRIN_H + +static __inline__ void + __attribute__((__always_inline__, __nodebug__, __target__("invpcid"))) +_invpcid(unsigned int __type, void *__descriptor) { + __builtin_ia32_invpcid(__type, __descriptor); +} + +#endif /* __INVPCIDINTRIN_H */ diff --git a/lib/Headers/module.modulemap b/lib/Headers/module.modulemap index b26ff5ebb5..1d1af57fd0 100644 --- a/lib/Headers/module.modulemap +++ b/lib/Headers/module.modulemap @@ -70,6 +70,7 @@ module _Builtin_intrinsics [system] [extern_c] { textual header "pconfigintrin.h" textual header "sgxintrin.h" textual header "ptwriteintrin.h" + textual header "invpcidintrin.h" textual header "__wmmintrin_aes.h" textual header "__wmmintrin_pclmul.h" diff --git a/test/CodeGen/invpcid.c b/test/CodeGen/invpcid.c new file mode 100644 index 0000000000..f472cd9953 --- /dev/null +++ b/test/CodeGen/invpcid.c @@ -0,0 +1,12 @@ +// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +invpcid -emit-llvm -o - -Wall -Werror -pedantic | FileCheck %s +// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +invpcid -emit-llvm -o - -Wall -Werror -pedantic | FileCheck %s + +#include + +#include + +void test_invpcid(uint32_t type, void *descriptor) { + //CHECK-LABEL: @test_invpcid + //CHECK: call void @llvm.x86.invpcid(i32 %{{.*}}, i8* %{{.*}}) + _invpcid(type, descriptor); +} diff --git a/test/Driver/x86-target-features.c b/test/Driver/x86-target-features.c index b7a1ead099..515ca425c2 100644 --- a/test/Driver/x86-target-features.c +++ b/test/Driver/x86-target-features.c @@ -164,3 +164,8 @@ // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-ptwrite %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-PTWRITE %s // PTWRITE: "-target-feature" "+ptwrite" // NO-PTWRITE: "-target-feature" "-ptwrite" + +// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -minvpcid %s -### -o %t.o 2>&1 | FileCheck -check-prefix=INVPCID %s +// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-invpcid %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-INVPCID %s +// INVPCID: "-target-feature" "+invpcid" +// NO-INVPCID: "-target-feature" "-invpcid" diff --git a/test/Preprocessor/predefined-arch-macros.c b/test/Preprocessor/predefined-arch-macros.c index 0a1e64230d..281e6780cb 100644 --- a/test/Preprocessor/predefined-arch-macros.c +++ b/test/Preprocessor/predefined-arch-macros.c @@ -526,6 +526,7 @@ // CHECK_CORE_AVX2_M32: #define __BMI__ 1 // CHECK_CORE_AVX2_M32: #define __F16C__ 1 // CHECK_CORE_AVX2_M32: #define __FMA__ 1 +// CHECK_CORE_AVX2_M32: #define __INVPCID__ 1 // CHECK_CORE_AVX2_M32: #define __LZCNT__ 1 // CHECK_CORE_AVX2_M32: #define __MMX__ 1 // CHECK_CORE_AVX2_M32: #define __PCLMUL__ 1 @@ -556,6 +557,7 @@ // CHECK_CORE_AVX2_M64: #define __BMI__ 1 // CHECK_CORE_AVX2_M64: #define __F16C__ 1 // CHECK_CORE_AVX2_M64: #define __FMA__ 1 +// CHECK_CORE_AVX2_M64: #define __INVPCID__ 1 // CHECK_CORE_AVX2_M64: #define __LZCNT__ 1 // CHECK_CORE_AVX2_M64: #define __MMX__ 1 // CHECK_CORE_AVX2_M64: #define __PCLMUL__ 1 @@ -590,6 +592,7 @@ // CHECK_BROADWELL_M32: #define __BMI__ 1 // CHECK_BROADWELL_M32: #define __F16C__ 1 // CHECK_BROADWELL_M32: #define __FMA__ 1 +// CHECK_BROADWELL_M32: #define __INVPCID__ 1 // CHECK_BROADWELL_M32: #define __LZCNT__ 1 // CHECK_BROADWELL_M32: #define __MMX__ 1 // CHECK_BROADWELL_M32: #define __PCLMUL__ 1 @@ -623,6 +626,7 @@ // CHECK_BROADWELL_M64: #define __BMI__ 1 // CHECK_BROADWELL_M64: #define __F16C__ 1 // CHECK_BROADWELL_M64: #define __FMA__ 1 +// CHECK_BROADWELL_M64: #define __INVPCID__ 1 // CHECK_BROADWELL_M64: #define __LZCNT__ 1 // CHECK_BROADWELL_M64: #define __MMX__ 1 // CHECK_BROADWELL_M64: #define __PCLMUL__ 1 @@ -660,6 +664,7 @@ // CHECK_SKL_M32: #define __CLFLUSHOPT__ 1 // CHECK_SKL_M32: #define __F16C__ 1 // CHECK_SKL_M32: #define __FMA__ 1 +// CHECK_SKL_M32: #define __INVPCID__ 1 // CHECK_SKL_M32: #define __LZCNT__ 1 // CHECK_SKL_M32: #define __MMX__ 1 // CHECK_SKL_M32: #define __MPX__ 1 @@ -694,6 +699,7 @@ // CHECK_SKL_M64: #define __CLFLUSHOPT__ 1 // CHECK_SKL_M64: #define __F16C__ 1 // CHECK_SKL_M64: #define __FMA__ 1 +// CHECK_SKL_M64: #define __INVPCID__ 1 // CHECK_SKL_M64: #define __LZCNT__ 1 // CHECK_SKL_M64: #define __MMX__ 1 // CHECK_SKL_M64: #define __MPX__ 1 @@ -888,6 +894,7 @@ // CHECK_SKX_M32: #define __CLWB__ 1 // CHECK_SKX_M32: #define __F16C__ 1 // CHECK_SKX_M32: #define __FMA__ 1 +// CHECK_SKX_M32: #define __INVPCID__ 1 // CHECK_SKX_M32: #define __LZCNT__ 1 // CHECK_SKX_M32: #define __MMX__ 1 // CHECK_SKX_M32: #define __MPX__ 1 @@ -933,6 +940,7 @@ // CHECK_SKX_M64: #define __CLWB__ 1 // CHECK_SKX_M64: #define __F16C__ 1 // CHECK_SKX_M64: #define __FMA__ 1 +// CHECK_SKX_M64: #define __INVPCID__ 1 // CHECK_SKX_M64: #define __LZCNT__ 1 // CHECK_SKX_M64: #define __MMX__ 1 // CHECK_SKX_M64: #define __MPX__ 1 @@ -983,6 +991,7 @@ // CHECK_CNL_M32-NOT: #define __CLWB__ 1 // CHECK_CNL_M32: #define __F16C__ 1 // CHECK_CNL_M32: #define __FMA__ 1 +// CHECK_CNL_M32: #define __INVPCID__ 1 // CHECK_CNL_M32: #define __LZCNT__ 1 // CHECK_CNL_M32: #define __MMX__ 1 // CHECK_CNL_M32: #define __MPX__ 1 @@ -1031,6 +1040,7 @@ // CHECK_CNL_M64-NOT: #define __CLWB__ 1 // CHECK_CNL_M64: #define __F16C__ 1 // CHECK_CNL_M64: #define __FMA__ 1 +// CHECK_CNL_M64: #define __INVPCID__ 1 // CHECK_CNL_M64: #define __LZCNT__ 1 // CHECK_CNL_M64: #define __MMX__ 1 // CHECK_CNL_M64: #define __MPX__ 1 @@ -1085,6 +1095,7 @@ // CHECK_ICL_M32: #define __F16C__ 1 // CHECK_ICL_M32: #define __FMA__ 1 // CHECK_ICL_M32: #define __GFNI__ 1 +// CHECK_ICL_M32: #define __INVPCID__ 1 // CHECK_ICL_M32: #define __LZCNT__ 1 // CHECK_ICL_M32: #define __MMX__ 1 // CHECK_ICL_M32: #define __MPX__ 1 @@ -1142,6 +1153,7 @@ // CHECK_ICL_M64: #define __F16C__ 1 // CHECK_ICL_M64: #define __FMA__ 1 // CHECK_ICL_M64: #define __GFNI__ 1 +// CHECK_ICL_M64: #define __INVPCID__ 1 // CHECK_ICL_M64: #define __LZCNT__ 1 // CHECK_ICL_M64: #define __MMX__ 1 // CHECK_ICL_M64: #define __MPX__ 1 @@ -1200,6 +1212,7 @@ // CHECK_ICX_M32: #define __F16C__ 1 // CHECK_ICX_M32: #define __FMA__ 1 // CHECK_ICX_M32: #define __GFNI__ 1 +// CHECK_ICX_M32: #define __INVPCID__ 1 // CHECK_ICX_M32: #define __LZCNT__ 1 // CHECK_ICX_M32: #define __MMX__ 1 // CHECK_ICX_M32: #define __MPX__ 1 @@ -1258,6 +1271,7 @@ // CHECK_ICX_M64: #define __F16C__ 1 // CHECK_ICX_M64: #define __FMA__ 1 // CHECK_ICX_M64: #define __GFNI__ 1 +// CHECK_ICX_M64: #define __INVPCID__ 1 // CHECK_ICX_M64: #define __LZCNT__ 1 // CHECK_ICX_M64: #define __MMX__ 1 // CHECK_ICX_M64: #define __MPX__ 1