From: Sanjay Patel <spatel@rotateright.com>
Date: Sat, 9 Feb 2019 17:03:59 +0000 (+0000)
Subject: [TargetLowering] add tests to show effect of setcc sub->shift; NFC
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=70a10441b95ef578d92b2bd6e5d29bc8b3a6af04;p=llvm

[TargetLowering] add tests to show effect of setcc sub->shift; NFC

There's effectively no difference for the cases with variables.
We just trade a sub for an add on those. But the case with a
subtract from constant would require an extra move instruction
on x86, so this looks like a reasonable generic combine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353619 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index b933f032409..eae5a45906f 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -3075,7 +3075,6 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
                                 DAG.getConstant(0, dl, N0.getValueType()),
                                 Cond);
           // The shift is not valid if this is a bool (i1).
-          // TODO: This transform needs evidence to justify its existence.
           if (N0.getNode()->hasOneUse() && OpVT.getScalarSizeInBits() != 1) {
             assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
             auto &DL = DAG.getDataLayout();
diff --git a/test/CodeGen/X86/setcc-combine.ll b/test/CodeGen/X86/setcc-combine.ll
index c13d2f114cf..ed3dfcdd7b1 100644
--- a/test/CodeGen/X86/setcc-combine.ll
+++ b/test/CodeGen/X86/setcc-combine.ll
@@ -297,3 +297,41 @@ define i64 @sub_to_shift_to_add(i32 %x, i32 %y, i64 %s1, i64 %s2) {
   ret i64 %r
 }
 
+define <4 x float> @sub_to_shift_to_add_vec(<4 x i32> %x, <4 x i32> %y, <4 x float> %s1, <4 x float> %s2) {
+; SSE2-LABEL: sub_to_shift_to_add_vec:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    paddd %xmm1, %xmm1
+; SSE2-NEXT:    pcmpeqd %xmm0, %xmm1
+; SSE2-NEXT:    pand %xmm1, %xmm2
+; SSE2-NEXT:    pandn %xmm3, %xmm1
+; SSE2-NEXT:    por %xmm2, %xmm1
+; SSE2-NEXT:    movdqa %xmm1, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE41-LABEL: sub_to_shift_to_add_vec:
+; SSE41:       # %bb.0:
+; SSE41-NEXT:    paddd %xmm1, %xmm1
+; SSE41-NEXT:    pcmpeqd %xmm1, %xmm0
+; SSE41-NEXT:    blendvps %xmm0, %xmm2, %xmm3
+; SSE41-NEXT:    movaps %xmm3, %xmm0
+; SSE41-NEXT:    retq
+  %sub = sub <4 x i32> %x, %y
+  %cmp = icmp eq <4 x i32> %sub, %y
+  %r = select <4 x i1> %cmp, <4 x float> %s1, <4 x float> %s2
+  ret <4 x float> %r
+}
+
+define i64 @sub_constant_to_shift_to_add(i32 %x, i64 %s1, i64 %s2) {
+; CHECK-LABEL: sub_constant_to_shift_to_add:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    addl %edi, %edi
+; CHECK-NEXT:    cmpl $42, %edi
+; CHECK-NEXT:    cmovneq %rdx, %rax
+; CHECK-NEXT:    retq
+  %sub = sub i32 42, %x
+  %cmp = icmp eq i32 %sub, %x
+  %r = select i1 %cmp, i64 %s1, i64 %s2
+  ret i64 %r
+}
+