From: Craig Topper Date: Tue, 12 Feb 2019 06:14:16 +0000 (+0000) Subject: [X86] Remove the value type operand from the floating point load/store MemIntrinsicSD... X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=6fe96f2c964097a204f58510392a1e7c84cc5fed;p=llvm [X86] Remove the value type operand from the floating point load/store MemIntrinsicSDNodes. Use the MemoryVT instead. NFCI We already have the memory VT, we can just match from that during isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353797 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 1ea12c1ef34..4ff6140e8c6 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -17672,7 +17672,7 @@ SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, MMO = cast(StackSlot)->getMemOperand(); StackSlot = StackSlot.getOperand(1); } - SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; + SDValue Ops[] = { Chain, StackSlot }; SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, DL, Tys, Ops, SrcVT, MMO); @@ -17690,9 +17690,7 @@ SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, auto PtrVT = getPointerTy(MF.getDataLayout()); SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); Tys = DAG.getVTList(MVT::Other); - SDValue Ops[] = { - Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag - }; + SDValue Ops[] = { Chain, Result, StackSlot, InFlag }; MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), MachineMemOperand::MOStore, SSFISize, SSFISize); @@ -18023,7 +18021,7 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, MachineMemOperand::MOLoad, 8, 8); SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); - SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; + SDValue Ops[] = { Store, StackSlot }; SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, MVT::i64, MMO); @@ -18179,9 +18177,7 @@ X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, Chain = DAG.getStore(Chain, DL, Value, StackSlot, MachinePointerInfo::getFixedStack(MF, SSFI)); SDVTList Tys = DAG.getVTList(TheVT, MVT::Other); - SDValue Ops[] = { - Chain, StackSlot, DAG.getValueType(TheVT) - }; + SDValue Ops[] = { Chain, StackSlot }; unsigned FLDSize = TheVT.getStoreSize(); assert(FLDSize <= MemSize && "Stack slot not big enough"); diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index 154e429cf8e..73393494642 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -605,22 +605,22 @@ namespace llvm { /// This instruction implements SINT_TO_FP with the /// integer source in memory and FP reg result. This corresponds to the - /// X86::FILD*m instructions. It has three inputs (token chain, address, - /// and source type) and two outputs (FP value and token chain). FILD_FLAG - /// also produces a flag). + /// X86::FILD*m instructions. It has two inputs (token chain and address) + /// and two outputs (FP value and token chain). FILD_FLAG also produces a + /// flag). The integer source type is specified by the memory VT. FILD, FILD_FLAG, /// This instruction implements an extending load to FP stack slots. /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain - /// operand, ptr to load from, and a ValueType node indicating the type - /// to load to. + /// operand, and ptr to load from. The memory VT specifies the type to + /// load from. FLD, /// This instruction implements a truncating store to FP stack /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a - /// chain operand, value to store, address, and a ValueType to store it - /// as. + /// chain operand, value to store, and address. The memory VT specifies + /// the type to store as. FST, /// This instruction grabs the address of the next argument diff --git a/lib/Target/X86/X86InstrFPStack.td b/lib/Target/X86/X86InstrFPStack.td index 12d7068f33a..ef1a61e59f7 100644 --- a/lib/Target/X86/X86InstrFPStack.td +++ b/lib/Target/X86/X86InstrFPStack.td @@ -16,14 +16,11 @@ // FPStack specific DAG Nodes. //===----------------------------------------------------------------------===// -def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>, - SDTCisPtrTy<1>, - SDTCisVT<2, OtherVT>]>; -def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>, - SDTCisPtrTy<1>, - SDTCisVT<2, OtherVT>]>; -def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>, - SDTCisVT<2, OtherVT>]>; +def SDTX86Fld : SDTypeProfile<1, 1, [SDTCisFP<0>, + SDTCisPtrTy<1>]>; +def SDTX86Fst : SDTypeProfile<0, 2, [SDTCisFP<0>, + SDTCisPtrTy<1>]>; +def SDTX86Fild : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisPtrTy<1>]>; def SDTX86Fnstsw : SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; @@ -50,6 +47,43 @@ def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, [SDNPHasChain, SDNPMayStore, SDNPSideEffect, SDNPMemOperand]>; +def X86fstf32 : PatFrag<(ops node:$val, node:$ptr), + (X86fst node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::f32; +}]>; +def X86fstf64 : PatFrag<(ops node:$val, node:$ptr), + (X86fst node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::f64; +}]>; +def X86fstf80 : PatFrag<(ops node:$val, node:$ptr), + (X86fst node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::f80; +}]>; + +def X86fldf32 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::f32; +}]>; +def X86fldf64 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::f64; +}]>; +def X86fldf80 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::f80; +}]>; + +def X86fild16 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i16; +}]>; +def X86fild32 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i32; +}]>; +def X86fild64 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i64; +}]>; + +def X86fildflag64 : PatFrag<(ops node:$ptr), (X86fildflag node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i64; +}]>; + //===----------------------------------------------------------------------===// // FPStack pattern fragments //===----------------------------------------------------------------------===// @@ -182,44 +216,44 @@ def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), OneArgFPRW, [!if(Forward, (set RFP32:$dst, - (OpNode RFP32:$src1, (X86fild addr:$src2, i16))), + (OpNode RFP32:$src1, (X86fild16 addr:$src2))), (set RFP32:$dst, - (OpNode (X86fild addr:$src2, i16), RFP32:$src1)))]>; + (OpNode (X86fild16 addr:$src2), RFP32:$src1)))]>; def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), OneArgFPRW, [!if(Forward, (set RFP32:$dst, - (OpNode RFP32:$src1, (X86fild addr:$src2, i32))), + (OpNode RFP32:$src1, (X86fild32 addr:$src2))), (set RFP32:$dst, - (OpNode (X86fild addr:$src2, i32), RFP32:$src1)))]>; + (OpNode (X86fild32 addr:$src2), RFP32:$src1)))]>; def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), OneArgFPRW, [!if(Forward, (set RFP64:$dst, - (OpNode RFP64:$src1, (X86fild addr:$src2, i16))), + (OpNode RFP64:$src1, (X86fild16 addr:$src2))), (set RFP64:$dst, - (OpNode (X86fild addr:$src2, i16), RFP64:$src1)))]>; + (OpNode (X86fild16 addr:$src2), RFP64:$src1)))]>; def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), OneArgFPRW, [!if(Forward, (set RFP64:$dst, - (OpNode RFP64:$src1, (X86fild addr:$src2, i32))), + (OpNode RFP64:$src1, (X86fild32 addr:$src2))), (set RFP64:$dst, - (OpNode (X86fild addr:$src2, i32), RFP64:$src1)))]>; + (OpNode (X86fild32 addr:$src2), RFP64:$src1)))]>; def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), OneArgFPRW, [!if(Forward, (set RFP80:$dst, - (OpNode RFP80:$src1, (X86fild addr:$src2, i16))), + (OpNode RFP80:$src1, (X86fild16 addr:$src2))), (set RFP80:$dst, - (OpNode (X86fild addr:$src2, i16), RFP80:$src1)))]>; + (OpNode (X86fild16 addr:$src2), RFP80:$src1)))]>; def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), OneArgFPRW, [!if(Forward, (set RFP80:$dst, - (OpNode RFP80:$src1, (X86fild addr:$src2, i32))), + (OpNode RFP80:$src1, (X86fild32 addr:$src2))), (set RFP80:$dst, - (OpNode (X86fild addr:$src2, i32), RFP80:$src1)))]>; + (OpNode (X86fild32 addr:$src2), RFP80:$src1)))]>; def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src), !strconcat("fi", asmstring, "{s}\t$src")>; def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), @@ -431,23 +465,23 @@ def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP, def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP, [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>; def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP, - [(set RFP32:$dst, (X86fild addr:$src, i16))]>; + [(set RFP32:$dst, (X86fild16 addr:$src))]>; def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP, - [(set RFP32:$dst, (X86fild addr:$src, i32))]>; + [(set RFP32:$dst, (X86fild32 addr:$src))]>; def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP, - [(set RFP32:$dst, (X86fild addr:$src, i64))]>; + [(set RFP32:$dst, (X86fild64 addr:$src))]>; def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP, - [(set RFP64:$dst, (X86fild addr:$src, i16))]>; + [(set RFP64:$dst, (X86fild16 addr:$src))]>; def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP, - [(set RFP64:$dst, (X86fild addr:$src, i32))]>; + [(set RFP64:$dst, (X86fild32 addr:$src))]>; def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP, - [(set RFP64:$dst, (X86fild addr:$src, i64))]>; + [(set RFP64:$dst, (X86fild64 addr:$src))]>; def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP, - [(set RFP80:$dst, (X86fild addr:$src, i16))]>; + [(set RFP80:$dst, (X86fild16 addr:$src))]>; def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP, - [(set RFP80:$dst, (X86fild addr:$src, i32))]>; + [(set RFP80:$dst, (X86fild32 addr:$src))]>; def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP, - [(set RFP80:$dst, (X86fild addr:$src, i64))]>; + [(set RFP80:$dst, (X86fild64 addr:$src))]>; } // SchedRW let SchedRW = [WriteStore], Uses = [FPCW] in { @@ -691,21 +725,17 @@ def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaquemem:$src), //===----------------------------------------------------------------------===// // Required for RET of f32 / f64 / f80 values. -def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>; -def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>; -def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>; +def : Pat<(X86fldf32 addr:$src), (LD_Fp32m addr:$src)>; +def : Pat<(X86fldf64 addr:$src), (LD_Fp64m addr:$src)>; +def : Pat<(X86fldf80 addr:$src), (LD_Fp80m addr:$src)>; // Required for CALL which return f32 / f64 / f80 values. -def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>; -def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, - RFP64:$src)>; -def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>; -def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op, - RFP80:$src)>; -def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op, - RFP80:$src)>; -def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op, - RFP80:$src)>; +def : Pat<(X86fstf32 RFP32:$src, addr:$op), (ST_Fp32m addr:$op, RFP32:$src)>; +def : Pat<(X86fstf32 RFP64:$src, addr:$op), (ST_Fp64m32 addr:$op, RFP64:$src)>; +def : Pat<(X86fstf64 RFP64:$src, addr:$op), (ST_Fp64m addr:$op, RFP64:$src)>; +def : Pat<(X86fstf32 RFP80:$src, addr:$op), (ST_Fp80m32 addr:$op, RFP80:$src)>; +def : Pat<(X86fstf64 RFP80:$src, addr:$op), (ST_Fp80m64 addr:$op, RFP80:$src)>; +def : Pat<(X86fstf80 RFP80:$src, addr:$op), (ST_FpP80m addr:$op, RFP80:$src)>; // Floating point constant -0.0 and -1.0 def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>; @@ -716,7 +746,7 @@ def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>; def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>; // Used to conv. i64 to f64 since there isn't a SSE version. -def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>; +def : Pat<(X86fildflag64 addr:$src), (ILD_Fp64m64 addr:$src)>; // FP extensions map onto simple pseudo-value conversions if they are to/from // the FP stack.