From: Craig Topper <craig.topper@intel.com>
Date: Sat, 28 Oct 2017 06:10:03 +0000 (+0000)
Subject: [X86] Add a fast-isel test for the i8 pseudo cmov.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=6fd0bcdf51d8d1d6000c93332fef46904993b065;p=llvm

[X86] Add a fast-isel test for the i8 pseudo cmov.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316827 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll b/test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll
index b5c879f654b..8724b66c911 100644
--- a/test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll
+++ b/test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll
@@ -277,3 +277,17 @@ define float @select_icmp_sle_f32(i64 %a, i64 %b, float %c, float %d) {
   ret float %2
 }
 
+define i8 @select_icmp_sle_i8(i64 %a, i64 %b, i8 %c, i8 %d) {
+; CHECK-LABEL: select_icmp_sle_i8:
+; CHECK:       ## BB#0:
+; CHECK-NEXT:    cmpq %rsi, %rdi
+; CHECK-NEXT:    jle LBB12_2
+; CHECK-NEXT:  ## BB#1:
+; CHECK-NEXT:    movl %ecx, %edx
+; CHECK-NEXT:  LBB12_2:
+; CHECK-NEXT:    movl %edx, %eax
+; CHECK-NEXT:    retq
+  %1 = icmp sle i64 %a, %b
+  %2 = select i1 %1, i8 %c, i8 %d
+  ret i8 %2
+}