From: Jack Carter <jcarter@mips.com>
Date: Tue, 21 Aug 2012 00:59:48 +0000 (+0000)
Subject: When this test case was first created it was
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=6e8686794e12b76f822fa71266a2cd76459e6a9a;p=clang

When this test case was first created it was
just trying to show it did not crash and burn.

This patch checks that the resultant .ll contents
are correct.


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@162249 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/mips-constraint-regs.c b/test/CodeGen/mips-constraint-regs.c
index 075be058dc..379dd4affd 100644
--- a/test/CodeGen/mips-constraint-regs.c
+++ b/test/CodeGen/mips-constraint-regs.c
@@ -1,4 +1,5 @@
-// RUN: %clang -target mipsel-unknown-linux -ccc-clang-archs mipsel -S -o - -emit-llvm %s
+// RUN: %clang -target mipsel-unknown-linux -ccc-clang-archs mipsel -S -o - -emit-llvm %s \
+// RUN: | FileCheck %s
 
 // This checks that the frontend will accept inline asm constraints
 // c', 'l' and 'x'. Semantic checking will happen in the
@@ -10,6 +11,7 @@ int main()
   // 'c': 16 bit address register for Mips16, GPR for all others
   // I am using 'c' to constrain both the target and one of the source
   // registers. We are looking for syntactical correctness.
+  // CHECK: %{{[0-9]+}} = call i32 asm sideeffect "addi $0,$1,$2 \0A\09\09", "=c,c,I"(i32 %{{[0-9]+}}, i32 %{{[0-9]+}}) nounwind, !srcloc !{{[0-9]+}}
   int __s, __v = 17;
   int __t;
   __asm__ __volatile__(
@@ -20,6 +22,7 @@ int main()
   // 'l': lo register
   // We are making it clear that destination register is lo with the
   // use of the 'l' constraint ("=l").
+  // CHECK:   %{{[0-9]+}} = call i32 asm sideeffect "mtlo $1 \0A\09\09", "=l,r,~{lo}"(i32 %{{[0-9]+}}) nounwind, !srcloc !{{[0-9]+}}
   int i_temp = 44;
   int i_result;
   __asm__ __volatile__(
@@ -31,6 +34,7 @@ int main()
   // 'x': Combined lo/hi registers
   // We are specifying that destination registers are the hi/lo pair with the
   // use of the 'x' constraint ("=x").
+  // CHECK:  %{{[0-9]+}} = call i64 asm sideeffect "mthi $1 \0A\09\09mtlo $2 \0A\09\09", "=x,r,r"(i32 %{{[0-9]+}}, i32 %{{[0-9]+}}) nounwind, !srcloc !{{[0-9]+}}
   int i_hi = 3;
   int i_lo = 2;
   long long ll_result = 0;
@@ -40,5 +44,6 @@ int main()
       : "=x" (ll_result)
         : "r" (i_hi), "r" (i_lo)
           : );
+
   return 0;
 }