From: Simon Atanasyan Date: Wed, 15 May 2019 12:05:27 +0000 (+0000) Subject: [mips] LLVM and GAS now use same instructions for CFA Definition. NFCI X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=6e7af205f8e0d5ecd134ee4d624816287e9623a1;p=llvm [mips] LLVM and GAS now use same instructions for CFA Definition. NFCI LLVM previously used `DW_CFA_def_cfa` instruction in .eh_frame to set the register and offset for current CFA rule. We change it to `DW_CFA_def_cfa_register` which is the same one used by GAS that only changes the register but keeping the old offset. Patch by Mirko Brkusanin. Differential Revision: https://reviews.llvm.org/D61899 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360765 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp index ac49a0eeb73..ddeec03ba78 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp @@ -85,7 +85,7 @@ static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, MCAsmInfo *MAI = new MipsMCAsmInfo(TT); unsigned SP = MRI.getDwarfRegNum(Mips::SP, true); - MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0); + MCCFIInstruction Inst = MCCFIInstruction::createDefCfaRegister(nullptr, SP); MAI->addInitialFrameState(Inst); return MAI; diff --git a/test/MC/Mips/cfi-advance-loc.s b/test/MC/Mips/cfi-advance-loc.s index 4f5666ab33c..407ad3faffe 100644 --- a/test/MC/Mips/cfi-advance-loc.s +++ b/test/MC/Mips/cfi-advance-loc.s @@ -37,7 +37,7 @@ g: // CHECK-LE-NEXT: EntrySize: 0 // CHECK-LE-NEXT: SectionData ( // CHECK-LE-NEXT: 0000: 10000000 00000000 017A5200 017C1F01 -// CHECK-LE-NEXT: 0010: 0B0C1D00 14000000 18000000 00000000 +// CHECK-LE-NEXT: 0010: 0B0D1D00 14000000 18000000 00000000 // CHECK-LE-NEXT: 0020: 04010000 00030001 0E080000 14000000 // CHECK-LE-NEXT: 0030: 30000000 04010000 04000100 00040000 // CHECK-LE-NEXT: 0040: 01000E08 @@ -60,7 +60,7 @@ g: // CHECK-BE-NEXT: EntrySize: 0 // CHECK-BE-NEXT: SectionData ( // CHECK-BE-NEXT: 0000: 00000010 00000000 017A5200 017C1F01 -// CHECK-BE-NEXT: 0010: 0B0C1D00 00000014 00000018 00000000 +// CHECK-BE-NEXT: 0010: 0B0D1D00 00000014 00000018 00000000 // CHECK-BE-NEXT: 0020: 00000104 00030100 0E080000 00000014 // CHECK-BE-NEXT: 0030: 00000030 00000104 00010004 00040001 // CHECK-BE-NEXT: 0040: 00000E08 diff --git a/test/MC/Mips/cfi-encoding.s b/test/MC/Mips/cfi-encoding.s index fe098076830..98a5ad1afe8 100644 --- a/test/MC/Mips/cfi-encoding.s +++ b/test/MC/Mips/cfi-encoding.s @@ -6,15 +6,15 @@ # RUN: | llvm-objdump -s -section=.eh_frame - | FileCheck --check-prefix=N64 %s # O32: 0000 00000010 00000000 017a5200 017c1f01 -# O32: 0010 0b0c1d00 00000010 00000018 00000000 +# O32: 0010 0b0d1d00 00000010 00000018 00000000 # O32: 0020 00000004 00000000 # N32: 0000 00000010 00000000 017a5200 017c1f01 -# N32: 0010 0b0c1d00 00000010 00000018 00000000 +# N32: 0010 0b0d1d00 00000010 00000018 00000000 # N32: 0020 00000004 00000000 # N64: 0000 00000010 00000000 017a5200 01781f01 -# N64: 0010 0c0c1d00 00000018 00000018 00000000 +# N64: 0010 0c0d1d00 00000018 00000018 00000000 # N64: 0020 00000000 00000000 00000004 00000000 foo: diff --git a/test/MC/Mips/eh-frame.s b/test/MC/Mips/eh-frame.s index e03027a20a4..e901f44196d 100644 --- a/test/MC/Mips/eh-frame.s +++ b/test/MC/Mips/eh-frame.s @@ -31,8 +31,7 @@ func: // DWARF32: Return address column: 31 // DWARF32: Augmentation data: 0B // ^^ fde pointer encoding: DW_EH_PE_sdata4 -// DWARF32: DW_CFA_def_cfa: reg29 +0 -// FIXME: The instructions are different from the ones produces by gas. +// DWARF32: DW_CFA_def_cfa_register: reg29 // // DWARF32: 00000014 00000010 00000018 FDE cie=00000018 pc=00000000...00000000 // DWARF32: DW_CFA_nop: @@ -49,8 +48,7 @@ func: // DWARF64: Return address column: 31 // DWARF64: Augmentation data: 0C // ^^ fde pointer encoding: DW_EH_PE_sdata8 -// DWARF64: DW_CFA_def_cfa: reg29 +0 -// FIXME: The instructions are different from the ones produces by gas. +// DWARF64: DW_CFA_def_cfa_register: reg29 // // DWARF64: 00000014 00000018 00000018 FDE cie=00000018 pc=00000000...00000000 // DWARF64: DW_CFA_nop: