From: Cullen Rhodes Date: Fri, 17 May 2019 09:04:44 +0000 (+0000) Subject: [AArch64][SVE2] Asm: add integer multiply long instructions X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=6bfb15391bc8693aedbb40b09a7b3fdb709a1268;p=llvm [AArch64][SVE2] Asm: add integer multiply long instructions Summary: Patch adds support for indexed and unpredicated vectors forms of the following instructions: * SMULLB, SMULLT, UMULLB, UMULLT, SQDMULLB, SQDMULLT The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: rovka Differential Revision: https://reviews.llvm.org/D61936 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361002 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/AArch64/AArch64SVEInstrInfo.td b/lib/Target/AArch64/AArch64SVEInstrInfo.td index a300505eb0b..5685a75dd23 100644 --- a/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1066,4 +1066,22 @@ let Predicates = [HasSVE2] in { // SVE2 complex integer multiply-add defm CMLA_ZZZ : sve2_int_cmla<0b0, "cmla">; defm SQRDCMLAH_ZZZ : sve2_int_cmla<0b1, "sqrdcmlah">; + + // SVE2 integer multiply long (indexed) + defm SMULLB_ZZZI : sve2_int_mul_long_by_indexed_elem<0b000, "smullb">; + defm SMULLT_ZZZI : sve2_int_mul_long_by_indexed_elem<0b001, "smullt">; + defm UMULLB_ZZZI : sve2_int_mul_long_by_indexed_elem<0b010, "umullb">; + defm UMULLT_ZZZI : sve2_int_mul_long_by_indexed_elem<0b011, "umullt">; + + // SVE2 saturating multiply (indexed) + defm SQDMULLB_ZZZI : sve2_int_mul_long_by_indexed_elem<0b100, "sqdmullb">; + defm SQDMULLT_ZZZI : sve2_int_mul_long_by_indexed_elem<0b101, "sqdmullt">; + + // SVE2 integer multiply long + defm SQDMULLB_ZZZ : sve2_wide_int_arith_long<0b11000, "sqdmullb">; + defm SQDMULLT_ZZZ : sve2_wide_int_arith_long<0b11001, "sqdmullt">; + defm SMULLB_ZZZ : sve2_wide_int_arith_long<0b11100, "smullb">; + defm SMULLT_ZZZ : sve2_wide_int_arith_long<0b11101, "smullt">; + defm UMULLB_ZZZ : sve2_wide_int_arith_long<0b11110, "umullb">; + defm UMULLT_ZZZ : sve2_wide_int_arith_long<0b11111, "umullt">; } diff --git a/lib/Target/AArch64/SVEInstrFormats.td b/lib/Target/AArch64/SVEInstrFormats.td index 4c9b54a8e8d..8b07ccdba4b 100644 --- a/lib/Target/AArch64/SVEInstrFormats.td +++ b/lib/Target/AArch64/SVEInstrFormats.td @@ -2009,6 +2009,52 @@ multiclass sve2_int_mul_by_indexed_elem opc, string asm> { } } +multiclass sve2_int_mul_long_by_indexed_elem opc, string asm> { + def _S : sve2_int_mul_by_indexed_elem<0b10, { opc{2-1}, ?, opc{0} }, asm, + ZPR32, ZPR16, ZPR3b16, VectorIndexH> { + bits<3> Zm; + bits<3> iop; + let Inst{20-19} = iop{2-1}; + let Inst{18-16} = Zm; + let Inst{11} = iop{0}; + } + def _D : sve2_int_mul_by_indexed_elem<0b11, { opc{2-1}, ?, opc{0} }, asm, + ZPR64, ZPR32, ZPR4b32, VectorIndexS> { + bits<4> Zm; + bits<2> iop; + let Inst{20} = iop{1}; + let Inst{19-16} = Zm; + let Inst{11} = iop{0}; + } +} + +//===----------------------------------------------------------------------===// +// SVE2 Widening Integer Arithmetic Group +//===----------------------------------------------------------------------===// + +class sve2_wide_int_arith sz, bits<5> opc, string asm, + ZPRRegOp zprty1, ZPRRegOp zprty2, ZPRRegOp zprty3> +: I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty3:$Zm), + asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + bits<5> Zm; + let Inst{31-24} = 0b01000101; + let Inst{23-22} = sz; + let Inst{21} = 0b0; + let Inst{20-16} = Zm; + let Inst{15} = 0b0; + let Inst{14-10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve2_wide_int_arith_long opc, string asm> { + def _H : sve2_wide_int_arith<0b01, opc, asm, ZPR16, ZPR8, ZPR8>; + def _S : sve2_wide_int_arith<0b10, opc, asm, ZPR32, ZPR16, ZPR16>; + def _D : sve2_wide_int_arith<0b11, opc, asm, ZPR64, ZPR32, ZPR32>; +} + //===----------------------------------------------------------------------===// // SVE Integer Arithmetic - Unary Predicated Group //===----------------------------------------------------------------------===// diff --git a/test/MC/AArch64/SVE2/smullb-diagnostics.s b/test/MC/AArch64/SVE2/smullb-diagnostics.s new file mode 100644 index 00000000000..9fe445dcd8f --- /dev/null +++ b/test/MC/AArch64/SVE2/smullb-diagnostics.s @@ -0,0 +1,106 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +smullb z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smullb z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smullb z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +smullb z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: smullb z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: smullb z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: smullb z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: smullb z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +smullb z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullb z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullb z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullb z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullb z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullb z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullb z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullb z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullb z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullb z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullb z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +smullb z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: smullb z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +smullb z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: smullb z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/smullb.s b/test/MC/AArch64/SVE2/smullb.s new file mode 100644 index 00000000000..259189df2ae --- /dev/null +++ b/test/MC/AArch64/SVE2/smullb.s @@ -0,0 +1,39 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +smullb z0.h, z1.b, z2.b +// CHECK-INST: smullb z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x70,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 70 42 45 + +smullb z29.s, z30.h, z31.h +// CHECK-INST: smullb z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x73,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 73 9f 45 + +smullb z31.d, z31.s, z31.s +// CHECK-INST: smullb z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x73,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 73 df 45 + +smullb z0.s, z1.h, z7.h[7] +// CHECK-INST: smullb z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xc8,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c8 bf 44 + +smullb z0.d, z1.s, z15.s[1] +// CHECK-INST: smullb z0.d, z1.s, z15.s[1] +// CHECK-ENCODING: [0x20,0xc8,0xef,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c8 ef 44 diff --git a/test/MC/AArch64/SVE2/smullt-diagnostics.s b/test/MC/AArch64/SVE2/smullt-diagnostics.s new file mode 100644 index 00000000000..42489d40243 --- /dev/null +++ b/test/MC/AArch64/SVE2/smullt-diagnostics.s @@ -0,0 +1,106 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +smullt z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smullt z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smullt z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +smullt z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: smullt z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: smullt z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: smullt z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: smullt z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +smullt z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullt z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullt z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullt z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullt z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullt z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullt z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullt z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullt z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullt z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullt z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +smullt z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: smullt z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +smullt z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: smullt z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/smullt.s b/test/MC/AArch64/SVE2/smullt.s new file mode 100644 index 00000000000..c5f488b264c --- /dev/null +++ b/test/MC/AArch64/SVE2/smullt.s @@ -0,0 +1,39 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +smullt z0.h, z1.b, z2.b +// CHECK-INST: smullt z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x74,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 74 42 45 + +smullt z29.s, z30.h, z31.h +// CHECK-INST: smullt z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x77,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 77 9f 45 + +smullt z31.d, z31.s, z31.s +// CHECK-INST: smullt z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x77,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 77 df 45 + +smullt z0.s, z1.h, z7.h[7] +// CHECK-INST: smullt z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xcc,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 cc bf 44 + +smullt z0.d, z1.s, z15.s[1] +// CHECK-INST: smullt z0.d, z1.s, z15.s[1] +// CHECK-ENCODING: [0x20,0xcc,0xef,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 cc ef 44 diff --git a/test/MC/AArch64/SVE2/sqdmullb-diagnostics.s b/test/MC/AArch64/SVE2/sqdmullb-diagnostics.s new file mode 100644 index 00000000000..879881d3200 --- /dev/null +++ b/test/MC/AArch64/SVE2/sqdmullb-diagnostics.s @@ -0,0 +1,106 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +sqdmullb z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmullb z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmullb z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +sqdmullb z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqdmullb z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqdmullb z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqdmullb z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqdmullb z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqdmullb z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullb z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullb z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullb z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullb z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullb z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullb z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullb z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullb z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullb z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullb z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +sqdmullb z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqdmullb z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sqdmullb z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqdmullb z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/sqdmullb.s b/test/MC/AArch64/SVE2/sqdmullb.s new file mode 100644 index 00000000000..ee992b0e6cc --- /dev/null +++ b/test/MC/AArch64/SVE2/sqdmullb.s @@ -0,0 +1,39 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sqdmullb z0.h, z1.b, z2.b +// CHECK-INST: sqdmullb z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x60,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 60 42 45 + +sqdmullb z29.s, z30.h, z31.h +// CHECK-INST: sqdmullb z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x63,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 63 9f 45 + +sqdmullb z31.d, z31.s, z31.s +// CHECK-INST: sqdmullb z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x63,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 63 df 45 + +sqdmullb z0.s, z1.h, z7.h[7] +// CHECK-INST: sqdmullb z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xe8,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 e8 bf 44 + +sqdmullb z0.d, z1.s, z15.s[1] +// CHECK-INST: sqdmullb z0.d, z1.s, z15.s[1] +// CHECK-ENCODING: [0x20,0xe8,0xef,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 e8 ef 44 diff --git a/test/MC/AArch64/SVE2/sqdmullt-diagnostics.s b/test/MC/AArch64/SVE2/sqdmullt-diagnostics.s new file mode 100644 index 00000000000..2a160bfe3a2 --- /dev/null +++ b/test/MC/AArch64/SVE2/sqdmullt-diagnostics.s @@ -0,0 +1,106 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +sqdmullt z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmullt z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmullt z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +sqdmullt z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqdmullt z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqdmullt z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqdmullt z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqdmullt z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqdmullt z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullt z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullt z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullt z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullt z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullt z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullt z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullt z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullt z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullt z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullt z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +sqdmullt z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqdmullt z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sqdmullt z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqdmullt z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/sqdmullt.s b/test/MC/AArch64/SVE2/sqdmullt.s new file mode 100644 index 00000000000..8bc7895b4b4 --- /dev/null +++ b/test/MC/AArch64/SVE2/sqdmullt.s @@ -0,0 +1,39 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sqdmullt z0.h, z1.b, z2.b +// CHECK-INST: sqdmullt z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x64,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 64 42 45 + +sqdmullt z29.s, z30.h, z31.h +// CHECK-INST: sqdmullt z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x67,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 67 9f 45 + +sqdmullt z31.d, z31.s, z31.s +// CHECK-INST: sqdmullt z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x67,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 67 df 45 + +sqdmullt z0.s, z1.h, z7.h[7] +// CHECK-INST: sqdmullt z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xec,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 ec bf 44 + +sqdmullt z0.d, z1.s, z15.s[1] +// CHECK-INST: sqdmullt z0.d, z1.s, z15.s[1] +// CHECK-ENCODING: [0x20,0xec,0xef,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 ec ef 44 diff --git a/test/MC/AArch64/SVE2/umullb-diagnostics.s b/test/MC/AArch64/SVE2/umullb-diagnostics.s new file mode 100644 index 00000000000..aca87a7635e --- /dev/null +++ b/test/MC/AArch64/SVE2/umullb-diagnostics.s @@ -0,0 +1,106 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +umullb z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umullb z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umullb z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +umullb z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: umullb z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: umullb z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: umullb z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: umullb z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +umullb z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullb z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullb z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullb z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullb z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullb z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullb z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullb z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullb z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullb z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullb z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +umullb z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: umullb z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +umullb z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: umullb z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/umullb.s b/test/MC/AArch64/SVE2/umullb.s new file mode 100644 index 00000000000..13ffcf520ec --- /dev/null +++ b/test/MC/AArch64/SVE2/umullb.s @@ -0,0 +1,39 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +umullb z0.h, z1.b, z2.b +// CHECK-INST: umullb z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x78,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 78 42 45 + +umullb z29.s, z30.h, z31.h +// CHECK-INST: umullb z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x7b,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 7b 9f 45 + +umullb z31.d, z31.s, z31.s +// CHECK-INST: umullb z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x7b,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 7b df 45 + +umullb z0.s, z1.h, z7.h[7] +// CHECK-INST: umullb z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xd8,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 d8 bf 44 + +umullb z0.d, z1.s, z15.s[1] +// CHECK-INST: umullb z0.d, z1.s, z15.s[1] +// CHECK-ENCODING: [0x20,0xd8,0xef,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 d8 ef 44 diff --git a/test/MC/AArch64/SVE2/umullt-diagnostics.s b/test/MC/AArch64/SVE2/umullt-diagnostics.s new file mode 100644 index 00000000000..80611e4df5b --- /dev/null +++ b/test/MC/AArch64/SVE2/umullt-diagnostics.s @@ -0,0 +1,106 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +umullt z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umullt z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umullt z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +umullt z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: umullt z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: umullt z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: umullt z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: umullt z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +umullt z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullt z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullt z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullt z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullt z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullt z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullt z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullt z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullt z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullt z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullt z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +umullt z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: umullt z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +umullt z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: umullt z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE2/umullt.s b/test/MC/AArch64/SVE2/umullt.s new file mode 100644 index 00000000000..72d9c9448d1 --- /dev/null +++ b/test/MC/AArch64/SVE2/umullt.s @@ -0,0 +1,39 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +umullt z0.h, z1.b, z2.b +// CHECK-INST: umullt z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x7c,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 7c 42 45 + +umullt z29.s, z30.h, z31.h +// CHECK-INST: umullt z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x7f,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 7f 9f 45 + +umullt z31.d, z31.s, z31.s +// CHECK-INST: umullt z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x7f,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 7f df 45 + +umullt z0.s, z1.h, z7.h[7] +// CHECK-INST: umullt z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xdc,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 dc bf 44 + +umullt z0.d, z1.s, z15.s[1] +// CHECK-INST: umullt z0.d, z1.s, z15.s[1] +// CHECK-ENCODING: [0x20,0xdc,0xef,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 dc ef 44