From: Amara Emerson <aemerson@apple.com>
Date: Sun, 8 Oct 2017 15:29:31 +0000 (+0000)
Subject: [AArch64][GlobalISel] Add a test case for G_PHI of p0 regbank selection.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=6a8905aab30b1072aa2bf76b9d6e335f1994e5a2;p=llvm

[AArch64][GlobalISel] Add a test case for G_PHI of p0 regbank selection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315178 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir b/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
index 82fb80c3bba..fe22db27087 100644
--- a/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
+++ b/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
@@ -66,6 +66,9 @@
 
   define void @test_fptosi_s64_s32() { ret void }
   define void @test_fptoui_s32_s64() { ret void }
+
+  define void @test_gphi_ptr() { ret void }
+
 ...
 
 ---
@@ -877,3 +880,42 @@ body: |
     %0(s64) = COPY %d0
     %1(s32) = G_FPTOUI %0
 ...
+
+---
+# CHECK-LABEL: name: test_gphi_ptr
+name:            test_gphi_ptr
+legalized:       true
+tracksRegLiveness: true
+# CHECK: registers:
+# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 2, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 3, class: gpr, preferred-register: '' }
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+  - { id: 2, class: _, preferred-register: '' }
+  - { id: 3, class: _, preferred-register: '' }
+  - { id: 4, class: _, preferred-register: '' }
+  - { id: 5, class: _, preferred-register: '' }
+body:             |
+  bb.0:
+    successors: %bb.1, %bb.2
+    liveins: %w2, %x0, %x1
+
+    %0(p0) = COPY %x0
+    %1(p0) = COPY %x1
+    %2(s1) = COPY %w2
+    G_BRCOND %2(s1), %bb.1
+    G_BR %bb.2
+
+  bb.1:
+    successors: %bb.2
+
+
+  bb.2:
+    %3(p0) = G_PHI %0(p0), %bb.0, %1(p0), %bb.1
+    %x0 = COPY %3(p0)
+    RET_ReallyLR implicit %x0
+
+...