From: Luo, Yuanke <yuanke.luo@intel.com>
Date: Thu, 11 Apr 2019 15:01:03 +0000 (+0000)
Subject: [X86] Add MM register mapping from CodeView to MC register id
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=6a2f99a8dea39ae6bb839efc21daf2ff4edeabdd;p=llvm

[X86] Add MM register mapping from CodeView to MC register id

Differential Revision: https://reviews.llvm.org/D60437

Change-Id: I2183a6d825d0284b22705d423b88882992b236c5

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358179 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
index 4a1f481f4a9..abd0d4b7ad6 100644
--- a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
+++ b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
@@ -116,6 +116,15 @@ void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) {
       {codeview::RegisterId::ST6, X86::FP6},
       {codeview::RegisterId::ST7, X86::FP7},
 
+      {codeview::RegisterId::MM0, X86::MM0},
+      {codeview::RegisterId::MM1, X86::MM1},
+      {codeview::RegisterId::MM2, X86::MM2},
+      {codeview::RegisterId::MM3, X86::MM3},
+      {codeview::RegisterId::MM4, X86::MM4},
+      {codeview::RegisterId::MM5, X86::MM5},
+      {codeview::RegisterId::MM6, X86::MM6},
+      {codeview::RegisterId::MM7, X86::MM7},
+
       {codeview::RegisterId::XMM0, X86::XMM0},
       {codeview::RegisterId::XMM1, X86::XMM1},
       {codeview::RegisterId::XMM2, X86::XMM2},