From: Ivan A. Kosarev <ikosarev@accesssoftek.com>
Date: Mon, 23 Jul 2018 16:01:35 +0000 (+0000)
Subject: [NEON] Define half-precision vmaxnm intrinsics only when available
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=697089101c24c2e1c46f0af39ad5d2dbdaa37ddf;p=clang

[NEON] Define half-precision vmaxnm intrinsics only when available

Differential Revision: https://reviews.llvm.org/D49375


git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@337704 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/clang/Basic/arm_neon.td b/include/clang/Basic/arm_neon.td
index ad7b3aecd3..d405aac106 100644
--- a/include/clang/Basic/arm_neon.td
+++ b/include/clang/Basic/arm_neon.td
@@ -1466,8 +1466,10 @@ let ArchGuard = "defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)" in {
   // Max/Min
   def VMAXH         : SInst<"vmax", "ddd", "hQh">;
   def VMINH         : SInst<"vmin", "ddd", "hQh">;
-  def FMAXNMH       : SInst<"vmaxnm", "ddd", "hQh">;
-  def FMINNMH       : SInst<"vminnm", "ddd", "hQh">;
+  let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_NUMERIC_MAXMIN) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)" in {
+    def FMAXNMH       : SInst<"vmaxnm", "ddd", "hQh">;
+    def FMINNMH       : SInst<"vminnm", "ddd", "hQh">;
+  }
 
   // Multiplication/Division
   def VMULH         : SOpInst<"vmul", "ddd", "hQh", OP_MUL>;
diff --git a/test/Sema/arm-no-fp16.c b/test/Sema/arm-no-fp16.c
index 2193c52fc5..2a23270e92 100644
--- a/test/Sema/arm-no-fp16.c
+++ b/test/Sema/arm-no-fp16.c
@@ -1,4 +1,6 @@
-// RUN: %clang_cc1 -triple thumbv7-none-eabi %s -target-feature +neon -target-feature -fp16 -fsyntax-only -verify
+// RUN: %clang_cc1 -triple thumbv7-none-eabi %s -target-feature +neon \
+// RUN:   -fallow-half-arguments-and-returns -target-feature -fp16 \
+// RUN:   -fsyntax-only -verify
 
 #include <arm_neon.h>
 
@@ -65,3 +67,19 @@ float16x4_t test_vrndx_f16(float16x4_t a) {
 float16x8_t test_vrndxq_f16(float16x8_t a) {
   return vrndxq_f16(a); // expected-warning{{implicit declaration of function 'vrndxq_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
 }
+
+float16x4_t test_vmaxnm_f16(float16x4_t a, float16x4_t b) {
+  return vmaxnm_f16(a, b); // expected-warning{{implicit declaration of function 'vmaxnm_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4_t'}}
+}
+
+float16x8_t test_vmaxnmq_f16(float16x8_t a, float16x8_t b) {
+  return vmaxnmq_f16(a, b); // expected-warning{{implicit declaration of function 'vmaxnmq_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vminnm_f16(float16x4_t a, float16x4_t b) {
+  return vminnm_f16(a, b); // expected-warning{{implicit declaration of function 'vminnm_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4_t'}}
+}
+
+float16x8_t test_vminnmq_f16(float16x8_t a, float16x8_t b) {
+  return vminnmq_f16(a, b); // expected-warning{{implicit declaration of function 'vminnmq_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
+}