From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Tue, 4 Jun 2019 10:17:56 +0000 (+0000)
Subject: [SelectionDAG] ComputeNumSignBits - clang-format + improve *EXTLOAD comments. NFCI.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=694eea2a3b5d936ff2dc36f2804295fdad494629;p=llvm

[SelectionDAG] ComputeNumSignBits - clang-format + improve *EXTLOAD comments. NFCI.

Pre-commit requested for D62777.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362485 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index e30b702ac15..4d854f81de2 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -3878,13 +3878,13 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
     if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
       unsigned ExtType = LD->getExtensionType();
       switch (ExtType) {
-        default: break;
-        case ISD::SEXTLOAD:    // '17' bits known
-          Tmp = LD->getMemoryVT().getScalarSizeInBits();
-          return VTBits-Tmp+1;
-        case ISD::ZEXTLOAD:    // '16' bits known
-          Tmp = LD->getMemoryVT().getScalarSizeInBits();
-          return VTBits-Tmp;
+      default: break;
+      case ISD::SEXTLOAD: // e.g. i16->i32 = '17' bits known.
+        Tmp = LD->getMemoryVT().getScalarSizeInBits();
+        return VTBits - Tmp + 1;
+      case ISD::ZEXTLOAD: // e.g. i16->i32 = '16' bits known.
+        Tmp = LD->getMemoryVT().getScalarSizeInBits();
+        return VTBits - Tmp;
       }
     }
   }