From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Fri, 21 Jun 2019 11:13:15 +0000 (+0000)
Subject: [X86] combineAndnp - use isNOT instead of manually checking for (XOR x, -1)
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=68d23994c8a87948dca67c452cf06c1ab509a135;p=llvm

[X86] combineAndnp - use isNOT instead of manually checking for (XOR x, -1)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364026 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index e15acc7d993..9c03f583be7 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -41023,11 +41023,9 @@ static SDValue combineAndnp(SDNode *N, SelectionDAG &DAG,
     return DAG.getConstant(0, SDLoc(N), VT);
 
   // Turn ANDNP back to AND if input is inverted.
-  if (VT.isVector() && N->getOperand(0).getOpcode() == ISD::XOR &&
-      ISD::isBuildVectorAllOnes(N->getOperand(0).getOperand(1).getNode())) {
-    return DAG.getNode(ISD::AND, SDLoc(N), VT,
-                       N->getOperand(0).getOperand(0), N->getOperand(1));
-  }
+  if (SDValue Not = IsNOT(N->getOperand(0), DAG))
+    return DAG.getNode(ISD::AND, SDLoc(N), VT, DAG.getBitcast(VT, Not),
+                       N->getOperand(1));
 
   // Attempt to recursively combine a bitmask ANDNP with shuffles.
   if (VT.isVector() && (VT.getScalarSizeInBits() % 8) == 0) {