From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Wed, 27 Mar 2019 16:12:29 +0000 (+0000)
Subject: AMDGPU: Don't hardcode num defs for MUBUF instructions
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=68048d45d3fe5deca5c145af8bbb1ea2aa74a86c;p=llvm

AMDGPU: Don't hardcode num defs for MUBUF instructions

This shouldn't change anything since the no-ret atomics are selected
later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357084 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/SIInstrInfo.cpp b/lib/Target/AMDGPU/SIInstrInfo.cpp
index 6155ad72f4c..7639a3fe138 100644
--- a/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -226,8 +226,8 @@ bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
     // getNamedOperandIdx returns the index for MachineInstrs.  Since they
     // include the output in the operand list, but SDNodes don't, we need to
     // subtract the index by one.
-    --OffIdx0;
-    --OffIdx1;
+    OffIdx0 -= get(Opc0).NumDefs;
+    OffIdx1 -= get(Opc1).NumDefs;
 
     SDValue Off0 = Load0->getOperand(OffIdx0);
     SDValue Off1 = Load1->getOperand(OffIdx1);