From: Craig Topper <craig.topper@intel.com>
Date: Mon, 23 Oct 2017 15:53:16 +0000 (+0000)
Subject: [X86] Add RDPID instruction for assembler and disassembler.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=63ea643e1fa7ae1bfb88db311a8583eed763e06e;p=llvm

[X86] Add RDPID instruction for assembler and disassembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316332 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 2cde6c02e95..05e47163c68 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -2195,13 +2195,13 @@ let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
   def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
                     "rdseed{w}\t$dst",
-                    [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
+                    [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, PS;
   def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
                     "rdseed{l}\t$dst",
-                    [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB;
+                    [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, PS;
   def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
                      "rdseed{q}\t$dst",
-                     [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
+                     [(set GR64:$dst, EFLAGS, (X86rdseed))]>, PS;
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/lib/Target/X86/X86InstrSystem.td b/lib/Target/X86/X86InstrSystem.td
index e9b6c6785bc..c95aa286152 100644
--- a/lib/Target/X86/X86InstrSystem.td
+++ b/lib/Target/X86/X86InstrSystem.td
@@ -635,3 +635,12 @@ let Defs = [EFLAGS] in {
 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
   def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, TB;
 }
+
+//===----------------------------------------------------------------------===//
+// RDPID Instruction
+def RDPID32 : I<0xC7, MRM7r, (outs GR32:$src), (ins),
+              "rdpid\t$src", []>, XS,
+              Requires<[Not64BitMode]>;
+def RDPID64 : I<0xC7, MRM7r, (outs GR64:$src), (ins),
+              "rdpid\t$src", []>, XS,
+              Requires<[In64BitMode]>;
diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt
index 620f2491970..86d9f92fbbf 100644
--- a/test/MC/Disassembler/X86/simple-tests.txt
+++ b/test/MC/Disassembler/X86/simple-tests.txt
@@ -964,3 +964,6 @@
 0x8f 0xe9 0x78 0x80 0x09
 # CHECK: vfrczps %ymm2, %ymm4
 0x8f 0xe9 0x7c 0x80 0xe2
+
+# CHECK: rdpid %rax
+0xf3 0x0f 0xc7 0xf8
diff --git a/test/MC/Disassembler/X86/x86-32.txt b/test/MC/Disassembler/X86/x86-32.txt
index bf73338ed4f..b069de2fd51 100644
--- a/test/MC/Disassembler/X86/x86-32.txt
+++ b/test/MC/Disassembler/X86/x86-32.txt
@@ -808,3 +808,6 @@
 0x2e 0x67 0x66 0x89 0x1c
 # CHECK: movw    %bx, %cs:(%si)
 0x2e 0x66 0x67 0x89 0x1c
+
+# CHECK: rdpid %eax
+0xf3 0x0f 0xc7 0xf8
diff --git a/test/MC/X86/x86-32.s b/test/MC/X86/x86-32.s
index 6cba31adbb4..80acbba6ce8 100644
--- a/test/MC/X86/x86-32.s
+++ b/test/MC/X86/x86-32.s
@@ -1097,3 +1097,7 @@ data16
 // CHECK: lgdtl 4(%eax)
 // CHECK:  encoding: [0x0f,0x01,0x50,0x04]
 data16 lgdt 4(%eax)
+
+// CHECK: rdpid %eax
+// CHECK: encoding: [0xf3,0x0f,0xc7,0xf8]
+rdpid %eax
diff --git a/test/MC/X86/x86-64.s b/test/MC/X86/x86-64.s
index d697428a2c0..96d775270b5 100644
--- a/test/MC/X86/x86-64.s
+++ b/test/MC/X86/x86-64.s
@@ -1527,3 +1527,7 @@ nopq	0xdeadbeef(%rbx,%rcx,8)
 // CHECK: nopq	%rax
 // CHECK:  encoding: [0x48,0x0f,0x1f,0xc0]
 nopq	%rax
+
+// CHECK: rdpid %rax
+// CHECK: encoding: [0xf3,0x0f,0xc7,0xf8]
+rdpid %rax