From: Marek Olsak <marek.olsak@amd.com>
Date: Tue, 24 Mar 2015 13:40:38 +0000 (+0000)
Subject: R600/SI: Insert more NOPs after READLANE on VI, don't use NOPs on CI
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=63d8e012ca865b0e81d0f2c178e288c5b2045fb8;p=llvm

R600/SI: Insert more NOPs after READLANE on VI, don't use NOPs on CI

This is a candidate for stable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233080 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/R600/SIRegisterInfo.cpp b/lib/Target/R600/SIRegisterInfo.cpp
index 6030ce8df46..13a89743677 100644
--- a/lib/Target/R600/SIRegisterInfo.cpp
+++ b/lib/Target/R600/SIRegisterInfo.cpp
@@ -268,7 +268,22 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
                   .addReg(SubReg);
         }
       }
-      TII->insertNOPs(MI, 3);
+
+      // TODO: only do this when it is needed
+      switch (MF->getSubtarget<AMDGPUSubtarget>().getGeneration()) {
+      case AMDGPUSubtarget::SOUTHERN_ISLANDS:
+        // "VALU writes SGPR" -> "SMRD reads that SGPR" needs "S_NOP 3" on SI
+        TII->insertNOPs(MI, 3);
+        break;
+      case AMDGPUSubtarget::SEA_ISLANDS:
+        break;
+      default: // VOLCANIC_ISLANDS and later
+        // "VALU writes SGPR -> VMEM reads that SGPR" needs "S_NOP 4" on VI
+        // and later. This also applies to VALUs which write VCC, but we're
+        // unlikely to see VMEM use VCC.
+        TII->insertNOPs(MI, 4);
+      }
+
       MI->eraseFromParent();
       break;
     }