From: Sanjay Patel <spatel@rotateright.com>
Date: Mon, 16 Jan 2017 19:23:34 +0000 (+0000)
Subject: [InstCombine] add tests to show missed vector folds; NFC
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=63bb8f30ce57d0de25070815cfc53621f7201f2f;p=llvm

[InstCombine] add tests to show missed vector folds; NFC

The shift-shift possibilities became easier to see after:
https://reviews.llvm.org/rL292145



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292150 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/Transforms/InstCombine/apint-shift.ll b/test/Transforms/InstCombine/apint-shift.ll
index d3dfc7f8f81..a46123529b4 100644
--- a/test/Transforms/InstCombine/apint-shift.ll
+++ b/test/Transforms/InstCombine/apint-shift.ll
@@ -113,19 +113,94 @@ define i19 @test10(i19 %X) {
   ret i19 %sh2
 }
 
-; FIXME: Same as above with vectors.
+; FIXME: Two right shifts in the same direction:
+; lshr (lshr X, C1), C2 --> lshr X, C1 + C2
+
+define <2 x i19> @lshr_lshr_splat_vec(<2 x i19> %X) {
+; CHECK-LABEL: @lshr_lshr_splat_vec(
+; CHECK-NEXT:    [[SH1:%.*]] = lshr <2 x i19> %X, <i19 3, i19 3>
+; CHECK-NEXT:    [[SH2:%.*]] = lshr <2 x i19> [[SH1]], <i19 2, i19 2>
+; CHECK-NEXT:    ret <2 x i19> [[SH2]]
+;
+  %sh1 = lshr <2 x i19> %X, <i19 3, i19 3>
+  %sh2 = lshr <2 x i19> %sh1, <i19 2, i19 2>
+  ret <2 x i19> %sh2
+}
+
+; FIXME: Two left shifts in the same direction:
+; shl (shl X, C1), C2 -->  shl X, C1 + C2
+
+define <2 x i19> @shl_shl_splat_vec(<2 x i19> %X) {
+; CHECK-LABEL: @shl_shl_splat_vec(
+; CHECK-NEXT:    [[SH1:%.*]] = shl <2 x i19> %X, <i19 3, i19 3>
+; CHECK-NEXT:    [[SH2:%.*]] = shl <2 x i19> [[SH1]], <i19 2, i19 2>
+; CHECK-NEXT:    ret <2 x i19> [[SH2]]
+;
+  %sh1 = shl <2 x i19> %X, <i19 3, i19 3>
+  %sh2 = shl <2 x i19> %sh1, <i19 2, i19 2>
+  ret <2 x i19> %sh2
+}
+
+; FIXME: Equal shift amounts in opposite directions become bitwise 'and':
+; lshr (shl X, C), C --> and X, C'
+
+define <2 x i19> @eq_shl_lshr_splat_vec(<2 x i19> %X) {
+; CHECK-LABEL: @eq_shl_lshr_splat_vec(
+; CHECK-NEXT:    [[SH1:%.*]] = shl <2 x i19> %X, <i19 3, i19 3>
+; CHECK-NEXT:    [[SH2:%.*]] = lshr exact <2 x i19> [[SH1]], <i19 3, i19 3>
+; CHECK-NEXT:    ret <2 x i19> [[SH2]]
+;
+  %sh1 = shl <2 x i19> %X, <i19 3, i19 3>
+  %sh2 = lshr <2 x i19> %sh1, <i19 3, i19 3>
+  ret <2 x i19> %sh2
+}
 
-define <2 x i19> @test10_splat_vec(<2 x i19> %X) {
-; CHECK-LABEL: @test10_splat_vec(
-; CHECK-NEXT:    [[SH1:%.*]] = lshr <2 x i19> %X, <i19 18, i19 18>
-; CHECK-NEXT:    [[SH2:%.*]] = shl nuw <2 x i19> [[SH1]], <i19 18, i19 18>
+; FIXME: Equal shift amounts in opposite directions become bitwise 'and':
+; shl (lshr X, C), C --> and X, C'
+
+define <2 x i19> @eq_lshr_shl_splat_vec(<2 x i19> %X) {
+; CHECK-LABEL: @eq_lshr_shl_splat_vec(
+; CHECK-NEXT:    [[SH1:%.*]] = lshr <2 x i19> %X, <i19 3, i19 3>
+; CHECK-NEXT:    [[SH2:%.*]] = shl nuw <2 x i19> [[SH1]], <i19 3, i19 3>
 ; CHECK-NEXT:    ret <2 x i19> [[SH2]]
 ;
-  %sh1 = lshr <2 x i19> %X, <i19 18, i19 18>
-  %sh2 = shl <2 x i19> %sh1, <i19 18, i19 18>
+  %sh1 = lshr <2 x i19> %X, <i19 3, i19 3>
+  %sh2 = shl <2 x i19> %sh1, <i19 3, i19 3>
   ret <2 x i19> %sh2
 }
 
+; FIXME: In general, we would need an 'and' for this transform, but the masked-off bits are known zero.
+; shl (lshr X, C1), C2 --> lshr X, C1 - C2
+
+define <2 x i7> @lshr_shl_splat_vec(<2 x i7> %X) {
+; CHECK-LABEL: @lshr_shl_splat_vec(
+; CHECK-NEXT:    [[MUL:%.*]] = mul <2 x i7> %X, <i7 -8, i7 -8>
+; CHECK-NEXT:    [[SH1:%.*]] = lshr exact <2 x i7> [[MUL]], <i7 3, i7 3>
+; CHECK-NEXT:    [[SH2:%.*]] = shl nuw nsw <2 x i7> [[SH1]], <i7 2, i7 2>
+; CHECK-NEXT:    ret <2 x i7> [[SH2]]
+;
+  %mul = mul <2 x i7> %X, <i7 -8, i7 -8>
+  %sh1 = lshr exact <2 x i7> %mul, <i7 3, i7 3>
+  %sh2 = shl nuw nsw <2 x i7> %sh1, <i7 2, i7 2>
+  ret <2 x i7> %sh2
+}
+
+; FIXME: In general, we would need an 'and' for this transform, but the masked-off bits are known zero.
+; lshr (shl X, C1), C2 -->  shl X, C1 - C2
+
+define <2 x i7> @shl_lshr_splat_vec(<2 x i7> %X) {
+; CHECK-LABEL: @shl_lshr_splat_vec(
+; CHECK-NEXT:    [[DIV:%.*]] = udiv <2 x i7> %X, <i7 9, i7 9>
+; CHECK-NEXT:    [[SH1:%.*]] = shl nuw <2 x i7> [[DIV]], <i7 3, i7 3>
+; CHECK-NEXT:    [[SH2:%.*]] = lshr exact <2 x i7> [[SH1]], <i7 2, i7 2>
+; CHECK-NEXT:    ret <2 x i7> [[SH2]]
+;
+  %div = udiv <2 x i7> %X, <i7 9, i7 9>
+  %sh1 = shl nuw <2 x i7> %div, <i7 3, i7 3>
+  %sh2 = lshr exact <2 x i7> %sh1, <i7 2, i7 2>
+  ret <2 x i7> %sh2
+}
+
 ; Don't hide the shl from scalar evolution. DAGCombine will get it.
 define i23 @test11(i23 %A) {
 ; CHECK-LABEL: @test11(