From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Sat, 30 Mar 2019 15:31:53 +0000 (+0000)
Subject: [X86][SSE] detectAVGPattern - begin generalizing ADD matches
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=63aa91b16e8710c79ff4c0bf11060d718b8d2a31;p=llvm

[X86][SSE] detectAVGPattern - begin generalizing ADD matches

Move the ADD matching into a helper - first NFC stage towards supporting 'ADD like' cases such as in PR41316


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357349 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 6f9caf1d0bb..6c62e661b5a 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -38203,12 +38203,23 @@ static SDValue detectAVGPattern(SDValue In, EVT VT, SelectionDAG &DAG,
                             AVGBuilder);
   }
 
-  if (Operands[0].getOpcode() == ISD::ADD)
+  // Matches 'add like' patterns.
+  // TODO: Extend this to include or/zext cases.
+  auto FindAddLike = [&](SDValue V, SDValue &Op0, SDValue &Op1) {
+    if (ISD::ADD != V.getOpcode())
+      return false;
+    Op0 = V.getOperand(0);
+    Op1 = V.getOperand(1);
+    return true;
+  };
+
+  SDValue Op0, Op1;
+  if (FindAddLike(Operands[0], Op0, Op1))
     std::swap(Operands[0], Operands[1]);
-  else if (Operands[1].getOpcode() != ISD::ADD)
+  else if (!FindAddLike(Operands[1], Op0, Op1))
     return SDValue();
-  Operands[2] = Operands[1].getOperand(0);
-  Operands[1] = Operands[1].getOperand(1);
+  Operands[2] = Op0;
+  Operands[1] = Op1;
 
   // Now we have three operands of two additions. Check that one of them is a
   // constant vector with ones, and the other two are promoted from i8/i16.