From: Simon Dardis Date: Wed, 12 Jul 2017 16:23:57 +0000 (+0000) Subject: [mips][mt][5/7] Add support for fork and yield instructions. X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=634bcaba6fa7a83b6fa8d3912d7cdb901ef244b3;p=llvm [mips][mt][5/7] Add support for fork and yield instructions. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35252 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307808 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Mips/MipsMTInstrFormats.td b/lib/Target/Mips/MipsMTInstrFormats.td index 81809cdf760..64bee5bfba1 100644 --- a/lib/Target/Mips/MipsMTInstrFormats.td +++ b/lib/Target/Mips/MipsMTInstrFormats.td @@ -49,3 +49,30 @@ class COP0_MFMC0_MT : MipsMTInst { let Inst{4-3} = 0b00; let Inst{2-0} = 0b001; } + +class SPECIAL3_MT_FORK : MipsMTInst { + bits<32> Inst; + + bits<5> rs; + bits<5> rt; + bits<5> rd; + let Inst{31-26} = 0b011111; // SPECIAL3 + let Inst{25-21} = rs; + let Inst{20-16} = rt; + let Inst{15-11} = rd; + let Inst{10-6} = 0b00000; + let Inst{5-0} = 0b001000; // FORK +} + +class SPECIAL3_MT_YIELD : MipsMTInst { + bits<32> Inst; + + bits<5> rs; + bits<5> rd; + let Inst{31-26} = 0b011111; // SPECIAL3 + let Inst{25-21} = rs; + let Inst{20-16} = 0b00000; + let Inst{15-11} = rd; + let Inst{10-6} = 0b00000; + let Inst{5-0} = 0b001001; // FORK +} diff --git a/lib/Target/Mips/MipsMTInstrInfo.td b/lib/Target/Mips/MipsMTInstrInfo.td index 722024b8c0b..ab6693f60fd 100644 --- a/lib/Target/Mips/MipsMTInstrInfo.td +++ b/lib/Target/Mips/MipsMTInstrInfo.td @@ -23,6 +23,10 @@ class DVPE_ENC : COP0_MFMC0_MT; +class FORK_ENC : SPECIAL3_MT_FORK; + +class YIELD_ENC : SPECIAL3_MT_YIELD; + //===----------------------------------------------------------------------===// // MIPS MT Instruction Descriptions //===----------------------------------------------------------------------===// @@ -35,6 +39,22 @@ class MT_1R_DESC_BASE { InstrItinClass Itinerary = Itin; } +class FORK_DESC { + dag OutOperandList = (outs GPR32Opnd:$rs, GPR32Opnd:$rd); + dag InOperandList = (ins GPR32Opnd:$rt); + string AsmString = "fork\t$rd, $rs, $rt"; + list Pattern = []; + InstrItinClass Itinerary = II_FORK; +} + +class YIELD_DESC { + dag OutOperandList = (outs GPR32Opnd:$rd); + dag InOperandList = (ins GPR32Opnd:$rs); + string AsmString = "yield\t$rd, $rs"; + list Pattern = []; + InstrItinClass Itinerary = II_YIELD; +} + class DMT_DESC : MT_1R_DESC_BASE<"dmt", II_DMT>; class EMT_DESC : MT_1R_DESC_BASE<"emt", II_EMT>; @@ -55,6 +75,10 @@ let hasSideEffects = 1, isNotDuplicable = 1, def DVPE : DVPE_ENC, DVPE_DESC, ASE_MT; def EVPE : EVPE_ENC, EVPE_DESC, ASE_MT; + + def FORK : FORK_ENC, FORK_DESC, ASE_MT; + + def YIELD : YIELD_ENC, YIELD_DESC, ASE_MT; } //===----------------------------------------------------------------------===// @@ -69,4 +93,6 @@ let AdditionalPredicates = [NotInMicroMips] in { def : MipsInstAlias<"dvpe", (DVPE ZERO), 1>, ASE_MT; def : MipsInstAlias<"evpe", (EVPE ZERO), 1>, ASE_MT; + + def : MipsInstAlias<"yield $rs", (YIELD ZERO, GPR32Opnd:$rs), 1>, ASE_MT; } diff --git a/lib/Target/Mips/MipsSchedule.td b/lib/Target/Mips/MipsSchedule.td index cc64f3cc9e4..c2947bb44ef 100644 --- a/lib/Target/Mips/MipsSchedule.td +++ b/lib/Target/Mips/MipsSchedule.td @@ -119,6 +119,7 @@ def II_EMT : InstrItinClass; def II_EVPE : InstrItinClass; def II_EXT : InstrItinClass; // Any EXT instruction def II_FLOOR : InstrItinClass; +def II_FORK : InstrItinClass; def II_INS : InstrItinClass; // Any INS instruction def II_IndirectBranchPseudo : InstrItinClass; // Indirect branch pseudo. def II_J : InstrItinClass; @@ -349,6 +350,7 @@ def II_WRPGPR : InstrItinClass; def II_RDPGPR : InstrItinClass; def II_DVP : InstrItinClass; def II_EVP : InstrItinClass; +def II_YIELD : InstrItinClass; //===----------------------------------------------------------------------===// // Mips Generic instruction itineraries. @@ -413,6 +415,7 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData]>, InstrItinData]>, InstrItinData]>, + InstrItinData]>, InstrItinData]>, InstrItinData]>, InstrItinData]>, @@ -678,5 +681,6 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData]>, InstrItinData]>, InstrItinData]>, - InstrItinData]> + InstrItinData]>, + InstrItinData]> ]>; diff --git a/lib/Target/Mips/MipsScheduleGeneric.td b/lib/Target/Mips/MipsScheduleGeneric.td index 12e42514658..89cda676441 100644 --- a/lib/Target/Mips/MipsScheduleGeneric.td +++ b/lib/Target/Mips/MipsScheduleGeneric.td @@ -187,7 +187,11 @@ def GenericIssueCOP0 : ProcResource<1> { let Super = GenericCOP0; } def GenericWriteCOP0TLB : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 4; } def GenericWriteCOP0 : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 3; } def GenericReadCOP0 : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 2; } -def GnereicReadWritePGPR : SchedWriteRes<[GenericIssueCOP0]>; +def GenericReadWritePGPR : SchedWriteRes<[GenericIssueCOP0]>; +def GenericReadWriteCOP0Long : SchedWriteRes<[GenericIssueCOP0]> { + let Latency = 5; +} +def GenericWriteCOP0Short : SchedWriteRes<[GenericIssueCOP0]>; def : ItinRW<[GenericWriteCOP0TLB], [II_TLBP, II_TLBR, II_TLBWI, II_TLBWR]>; def : ItinRW<[GenericWriteCOP0TLB], [II_TLBINV, II_TLBINVF]>; @@ -266,6 +270,8 @@ def : ItinRW<[GenericWriteLoad], [II_LWLE, II_LWRE]>; def : ItinRW<[GenericWriteMove], [II_DMT, II_DVPE, II_EMT, II_EVPE]>; +def : ItinRW<[GenericReadWriteCOP0Long], [II_YIELD]>; +def : ItinRW<[GenericWriteCOP0Short], [II_FORK]>; // MIPS32R6 and MIPS16e // ==================== diff --git a/test/MC/Disassembler/Mips/mt/valid-r2-el.txt b/test/MC/Disassembler/Mips/mt/valid-r2-el.txt index 7dc7414feb8..7025354d684 100644 --- a/test/MC/Disassembler/Mips/mt/valid-r2-el.txt +++ b/test/MC/Disassembler/Mips/mt/valid-r2-el.txt @@ -7,4 +7,7 @@ 0x01 0x00 0x66 0x41 # CHECK: dvpe $6 0x21 0x00 0x60 0x41 # CHECK: evpe 0x21 0x00 0x64 0x41 # CHECK: evpe $4 +0x08 0x10 0x65 0x7c # CHECK: fork $2, $3, $5 +0x09 0x00 0x80 0x7c # CHECK: yield $4 +0x09 0x20 0xa0 0x7c # CHECK: yield $4, $5 diff --git a/test/MC/Disassembler/Mips/mt/valid-r2.txt b/test/MC/Disassembler/Mips/mt/valid-r2.txt index 8f0fdb038ce..17c42c0614a 100644 --- a/test/MC/Disassembler/Mips/mt/valid-r2.txt +++ b/test/MC/Disassembler/Mips/mt/valid-r2.txt @@ -7,4 +7,7 @@ 0x41 0x66 0x00 0x01 # CHECK: dvpe $6 0x41 0x60 0x00 0x21 # CHECK: evpe 0x41 0x64 0x00 0x21 # CHECK: evpe $4 +0x7c 0x65 0x10 0x08 # CHECK: fork $2, $3, $5 +0x7c 0x80 0x00 0x09 # CHECK: yield $4 +0x7c 0xa0 0x20 0x09 # CHECK: yield $4, $5 diff --git a/test/MC/Mips/mt/valid.s b/test/MC/Mips/mt/valid.s index d75304d46d4..ab1179d05c6 100644 --- a/test/MC/Mips/mt/valid.s +++ b/test/MC/Mips/mt/valid.s @@ -8,4 +8,6 @@ dvpe $6 # CHECK: dvpe $6 # encoding: [0x41,0x66,0x00,0x01] evpe # CHECK: evpe # encoding: [0x41,0x60,0x00,0x21] evpe $4 # CHECK: evpe $4 # encoding: [0x41,0x64,0x00,0x21] - + fork $2, $3, $5 # CHECK: fork $2, $3, $5 # encoding: [0x7c,0x65,0x10,0x08] + yield $4 # CHECK: yield $4 # encoding: [0x7c,0x80,0x00,0x09] + yield $4, $5 # CHECK: yield $4, $5 # encoding: [0x7c,0xa0,0x20,0x09]