From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Tue, 18 Apr 2017 20:59:46 +0000 (+0000)
Subject: Fix typo
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=632c2834200b33571d51b91164efe5b8c6c44150;p=llvm

Fix typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300597 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/SIRegisterInfo.cpp b/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 36d4df52ff0..098c67252dd 100644
--- a/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -124,7 +124,7 @@ unsigned SIRegisterInfo::reservedPrivateSegmentWaveByteOffsetReg(
   unsigned RegCount = ST.getMaxNumSGPRs(MF);
   unsigned Reg;
 
-  // Try to place it in a hole after PrivateSegmentbufferReg.
+  // Try to place it in a hole after PrivateSegmentBufferReg.
   if (RegCount & 3) {
     // We cannot put the segment buffer in (Idx - 4) ... (Idx - 1) due to
     // alignment constraints, so we have a hole where can put the wave offset.