From: Kevin Enderby Date: Tue, 24 Jan 2017 23:41:04 +0000 (+0000) Subject: Fix llvm-objdump so it picks a good CPU based for Mach-O files X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=61fed38d4336c66ed8383481f20077335626a1c4;p=llvm Fix llvm-objdump so it picks a good CPU based for Mach-O files for CPU_SUBTYPE_ARM_V7S and CPU_SUBTYPE_ARM_V7K. For these two cpusubtypes they should default to a cortex-a7 CPU to give proper disassembly without a -mcpu= flag. rdar://27431703 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292993 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Object/MachOObjectFile.cpp b/lib/Object/MachOObjectFile.cpp index ae1ac097169..c0a7518d1e6 100644 --- a/lib/Object/MachOObjectFile.cpp +++ b/lib/Object/MachOObjectFile.cpp @@ -2454,6 +2454,8 @@ Triple MachOObjectFile::getArchTriple(uint32_t CPUType, uint32_t CPUSubType, *ArchFlag = "armv7em"; return Triple("thumbv7em-apple-darwin"); case MachO::CPU_SUBTYPE_ARM_V7K: + if (McpuDefault) + *McpuDefault = "cortex-a7"; if (ArchFlag) *ArchFlag = "armv7k"; return Triple("armv7k-apple-darwin"); @@ -2464,6 +2466,8 @@ Triple MachOObjectFile::getArchTriple(uint32_t CPUType, uint32_t CPUSubType, *ArchFlag = "armv7m"; return Triple("thumbv7m-apple-darwin"); case MachO::CPU_SUBTYPE_ARM_V7S: + if (McpuDefault) + *McpuDefault = "cortex-a7"; if (ArchFlag) *ArchFlag = "armv7s"; return Triple("armv7s-apple-darwin"); diff --git a/test/tools/llvm-objdump/ARM/Inputs/divs.macho-armv7s b/test/tools/llvm-objdump/ARM/Inputs/divs.macho-armv7s new file mode 100644 index 00000000000..b877d2d5180 Binary files /dev/null and b/test/tools/llvm-objdump/ARM/Inputs/divs.macho-armv7s differ diff --git a/test/tools/llvm-objdump/ARM/macho-nomcpu-armv7s.test b/test/tools/llvm-objdump/ARM/macho-nomcpu-armv7s.test new file mode 100644 index 00000000000..ff7daa8c214 --- /dev/null +++ b/test/tools/llvm-objdump/ARM/macho-nomcpu-armv7s.test @@ -0,0 +1,3 @@ +@ RUN: llvm-objdump -m -d %p/Inputs/divs.macho-armv7s | FileCheck %s + +@ CHECK: 10 f0 10 e7 sdiv r0, r0, r0