From: Simon Pilgrim Date: Sun, 18 Aug 2019 15:39:04 +0000 (+0000) Subject: [X86][SSE] Improve PACKSS shuffle tests to better match codegen from D61129 X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=60f429a1debbddab8b605a94a78747b2dc4efd82;p=llvm [X86][SSE] Improve PACKSS shuffle tests to better match codegen from D61129 D61129 creates 'concat + trunc' style patterns (at the 128-bit subvector level) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@369209 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/test/CodeGen/X86/packss.ll b/test/CodeGen/X86/packss.ll index e8729d14d84..3b7dd912efe 100644 --- a/test/CodeGen/X86/packss.ll +++ b/test/CodeGen/X86/packss.ll @@ -263,8 +263,8 @@ define <8 x i16> @trunc_ashr_v4i64_demandedelts(<4 x i64> %a0) { ret <8 x i16> %5 } -define <16 x i8> @packsswb_icmp_128_zero(<8 x i16> %a0) { -; SSE-LABEL: packsswb_icmp_128_zero: +define <16 x i8> @packsswb_icmp_zero_128(<8 x i16> %a0) { +; SSE-LABEL: packsswb_icmp_zero_128: ; SSE: # %bb.0: ; SSE-NEXT: pxor %xmm1, %xmm1 ; SSE-NEXT: pcmpeqw %xmm0, %xmm1 @@ -272,7 +272,7 @@ define <16 x i8> @packsswb_icmp_128_zero(<8 x i16> %a0) { ; SSE-NEXT: movq {{.*#+}} xmm0 = xmm1[0],zero ; SSE-NEXT: ret{{[l|q]}} ; -; AVX-LABEL: packsswb_icmp_128_zero: +; AVX-LABEL: packsswb_icmp_zero_128: ; AVX: # %bb.0: ; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 @@ -284,42 +284,106 @@ define <16 x i8> @packsswb_icmp_128_zero(<8 x i16> %a0) { ret <16 x i8> %3 } +define <16 x i8> @packsswb_icmp_zero_trunc_128(<8 x i16> %a0) { +; SSE-LABEL: packsswb_icmp_zero_trunc_128: +; SSE: # %bb.0: +; SSE-NEXT: pxor %xmm1, %xmm1 +; SSE-NEXT: pcmpeqw %xmm1, %xmm0 +; SSE-NEXT: packsswb %xmm1, %xmm0 +; SSE-NEXT: ret{{[l|q]}} +; +; AVX-LABEL: packsswb_icmp_zero_trunc_128: +; AVX: # %bb.0: +; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 +; AVX-NEXT: ret{{[l|q]}} + %1 = icmp eq <8 x i16> %a0, zeroinitializer + %2 = sext <8 x i1> %1 to <8 x i16> + %3 = shufflevector <8 x i16> %2, <8 x i16> zeroinitializer, <16 x i32> + %4 = trunc <16 x i16> %3 to <16 x i8> + ret <16 x i8> %4 +} + define <32 x i8> @packsswb_icmp_zero_256(<16 x i16> %a0) { ; SSE-LABEL: packsswb_icmp_zero_256: ; SSE: # %bb.0: ; SSE-NEXT: pxor %xmm2, %xmm2 ; SSE-NEXT: pcmpeqw %xmm2, %xmm1 ; SSE-NEXT: pcmpeqw %xmm2, %xmm0 -; SSE-NEXT: packsswb %xmm1, %xmm0 -; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3] -; SSE-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7] -; SSE-NEXT: movaps %xmm2, %xmm1 +; SSE-NEXT: packsswb %xmm0, %xmm0 +; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1] +; SSE-NEXT: packsswb %xmm1, %xmm1 +; SSE-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1] ; SSE-NEXT: ret{{[l|q]}} ; ; AVX1-LABEL: packsswb_icmp_zero_256: ; AVX1: # %bb.0: -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 -; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 -; AVX1-NEXT: vpcmpeqw %xmm2, %xmm1, %xmm1 -; AVX1-NEXT: vpacksswb %xmm1, %xmm0, %xmm1 -; AVX1-NEXT: vpcmpeqw %xmm2, %xmm0, %xmm0 -; AVX1-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 -; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7] +; AVX1-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 +; AVX1-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [128,128,128,128,128,128,128,128,0,2,4,6,8,10,12,14] +; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpshufb %xmm1, %xmm2, %xmm1 +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: ret{{[l|q]}} ; ; AVX2-LABEL: packsswb_icmp_zero_256: ; AVX2: # %bb.0: ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX2-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0 -; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2 -; AVX2-NEXT: vpacksswb %xmm2, %xmm0, %xmm0 -; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,0,2,1] -; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7] +; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,zero,ymm0[0,2,4,6,8,10,12,14],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,18,20,22,24,26,28,30] +; AVX2-NEXT: ret{{[l|q]}} + %1 = icmp eq <16 x i16> %a0, zeroinitializer + %2 = sext <16 x i1> %1 to <16 x i16> + %3 = bitcast <16 x i16> %2 to <32 x i8> + %4 = shufflevector <32 x i8> zeroinitializer, <32 x i8> %3, <32 x i32> + ret <32 x i8> %4 +} + +define <32 x i8> @packsswb_icmp_zero_trunc_256(<16 x i16> %a0) { +; SSE-LABEL: packsswb_icmp_zero_trunc_256: +; SSE: # %bb.0: +; SSE-NEXT: pxor %xmm2, %xmm2 +; SSE-NEXT: pcmpeqw %xmm2, %xmm1 +; SSE-NEXT: pcmpeqw %xmm2, %xmm0 +; SSE-NEXT: pxor %xmm3, %xmm3 +; SSE-NEXT: packsswb %xmm0, %xmm3 +; SSE-NEXT: packsswb %xmm1, %xmm2 +; SSE-NEXT: movdqa %xmm3, %xmm0 +; SSE-NEXT: movdqa %xmm2, %xmm1 +; SSE-NEXT: ret{{[l|q]}} +; +; AVX1-LABEL: packsswb_icmp_zero_trunc_256: +; AVX1: # %bb.0: +; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; AVX1-NEXT: vpcmpeqw %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpcmpeqw %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: vperm2f128 {{.*#+}} ymm2 = zero,zero,ymm0[0,1] +; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7] +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm1 +; AVX1-NEXT: vpacksswb %xmm1, %xmm2, %xmm1 +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: ret{{[l|q]}} +; +; AVX2-LABEL: packsswb_icmp_zero_trunc_256: +; AVX2: # %bb.0: +; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX2-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] +; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = zero,zero,ymm0[0,1] +; AVX2-NEXT: vpacksswb %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3] ; AVX2-NEXT: ret{{[l|q]}} %1 = icmp eq <16 x i16> %a0, zeroinitializer - %2 = sext <16 x i1> %1 to <16 x i8> - %3 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %2, <32 x i32> - ret <32 x i8> %3 + %2 = sext <16 x i1> %1 to <16 x i16> + %3 = shufflevector <16 x i16> zeroinitializer, <16 x i16> %2, <32 x i32> + %4 = trunc <32 x i16> %3 to <32 x i8> + ret <32 x i8> %4 }