From: Craig Topper <craig.topper@intel.com>
Date: Sat, 14 Oct 2017 04:18:09 +0000 (+0000)
Subject: [X86] Add additional patterns for folding loads with 128-bit VCVTDQ2PD and VCVTUDQ2PD.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=60273a80213af332e8a7ecd8a7e074bdbfd2095d;p=llvm

[X86] Add additional patterns for folding loads with 128-bit VCVTDQ2PD and VCVTUDQ2PD.

This matches the patterns we have for the SSE/AVX version.

This is a prerequisite for D38714.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315797 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td
index b3eb34bf44c..d73abf08105 100644
--- a/lib/Target/X86/X86InstrAVX512.td
+++ b/lib/Target/X86/X86InstrAVX512.td
@@ -7055,6 +7055,16 @@ let Predicates = [HasAVX512, HasVLX] in {
                                  (v4i32 (X86cvttp2ui (v2f64 VR128X:$src)))))))),
               (VCVTTPD2UDQZ128rr VR128X:$src)>;
   }
+
+  def : Pat<(v2f64 (X86VSintToFP (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
+            (VCVTDQ2PDZ128rm addr:$src)>;
+  def : Pat<(v2f64 (X86VSintToFP (bc_v4i32 (v2i64 (X86vzload addr:$src))))),
+            (VCVTDQ2PDZ128rm addr:$src)>;
+
+  def : Pat<(v2f64 (X86VUintToFP (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
+            (VCVTUDQ2PDZ128rm addr:$src)>;
+  def : Pat<(v2f64 (X86VUintToFP (bc_v4i32 (v2i64 (X86vzload addr:$src))))),
+            (VCVTUDQ2PDZ128rm addr:$src)>;
 }
 
 let Predicates = [HasAVX512] in {