From: Simon Pilgrim Date: Wed, 13 Mar 2019 11:08:57 +0000 (+0000) Subject: [DAG] Move integer setcc %x, %x folding into FoldSetCC X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=5fd3b9019a6aca17489bf7f4923e2ac0e63829e2;p=llvm [DAG] Move integer setcc %x, %x folding into FoldSetCC First step towards PR40800 - I intend to move the float case in a separate future patch. I had to tweak the (overly reduced) thumb2 test and the x86 widening test change is annoying (no longer rematerializable) but we should address this separately. Differential Revision: https://reviews.llvm.org/D59244 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356040 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index a87883bbe40..fe3f2b99ba7 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1974,6 +1974,10 @@ SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1, SDValue N2, break; } + // We can always fold X == X for integer setcc's. + if (N1 == N2 && OpVT.isInteger()) + return getBoolConstant(ISD::isTrueWhenEqual(Cond), dl, VT, OpVT); + if (ConstantSDNode *N2C = dyn_cast(N2)) { const APInt &C2 = N2C->getAPIntValue(); if (ConstantSDNode *N1C = dyn_cast(N1)) { diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 06596dbaf70..2a1b9745490 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -3004,13 +3004,10 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, if (N0 == N1) { // The sext(setcc()) => setcc() optimization relies on the appropriate // constant being emitted. + assert(!N0.getValueType().isInteger() && + "Integer types should be handled by FoldSetCC"); bool EqTrue = ISD::isTrueWhenEqual(Cond); - - // We can always fold X == X for integer setcc's. - if (N0.getValueType().isInteger()) - return DAG.getBoolConstant(EqTrue, dl, VT, OpVT); - unsigned UOF = ISD::getUnorderedFlavor(Cond); if (UOF == 2) // FP operators that are undefined on NaNs. return DAG.getBoolConstant(EqTrue, dl, VT, OpVT); diff --git a/test/CodeGen/AArch64/fast-isel-cmp-vec.ll b/test/CodeGen/AArch64/fast-isel-cmp-vec.ll index 42112065943..6e532fdb9eb 100644 --- a/test/CodeGen/AArch64/fast-isel-cmp-vec.ll +++ b/test/CodeGen/AArch64/fast-isel-cmp-vec.ll @@ -24,10 +24,8 @@ bb2: define <2 x i32> @icmp_constfold_v2i32(<2 x i32> %a) { ; CHECK-LABEL: icmp_constfold_v2i32: ; CHECK: ; %bb.0: -; CHECK-NEXT: movi.2d v[[CMP:[0-9]+]], #0xffffffffffffffff -; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: movi.2s [[MASK:v[0-9]+]], #1 -; CHECK-NEXT: and.8b v0, v[[CMP]], [[MASK]] +; CHECK-NEXT: and.8b v0, [[MASK]], [[MASK]] ; CHECK-NEXT: ret %1 = icmp eq <2 x i32> %a, %a br label %bb2 @@ -56,10 +54,9 @@ bb2: define <4 x i32> @icmp_constfold_v4i32(<4 x i32> %a) { ; CHECK-LABEL: icmp_constfold_v4i32: ; CHECK: ; %bb.0: -; CHECK-NEXT: movi.2d v[[CMP:[0-9]+]], #0xffffffffffffffff -; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: movi.4h [[MASK:v[0-9]+]], #1 -; CHECK-NEXT: and.8b [[ZEXT:v[0-9]+]], v[[CMP]], [[MASK]] +; CHECK-NEXT: ; %bb.1: +; CHECK-NEXT: and.8b [[ZEXT:v[0-9]+]], [[MASK]], [[MASK]] ; CHECK-NEXT: ushll.4s v0, [[ZEXT]], #0 ; CHECK-NEXT: ret %1 = icmp eq <4 x i32> %a, %a @@ -87,10 +84,8 @@ bb2: define <16 x i8> @icmp_constfold_v16i8(<16 x i8> %a) { ; CHECK-LABEL: icmp_constfold_v16i8: ; CHECK: ; %bb.0: -; CHECK-NEXT: movi.2d [[CMP:v[0-9]+]], #0xffffffffffffffff -; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: movi.16b [[MASK:v[0-9]+]], #1 -; CHECK-NEXT: and.16b v0, [[CMP]], [[MASK]] +; CHECK-NEXT: and.16b v0, [[MASK]], [[MASK]] ; CHECK-NEXT: ret %1 = icmp eq <16 x i8> %a, %a br label %bb2 diff --git a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll index 3a22c4a2094..b9ec0b43f55 100644 --- a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll +++ b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll @@ -64,7 +64,7 @@ bb8: ; preds = %bb8, %bb7 %32 = fsub float %30, %31 ; [#uses=1] %33 = fsub float %10, %32 ; [#uses=1] store float %33, float* undef, align 4 - %34 = icmp slt i32 undef, undef ; [#uses=1] + %34 = icmp slt i32 %tmp54, %tmp80 ; [#uses=1] br i1 %34, label %bb8, label %bb9 bb9: ; preds = %bb8 diff --git a/test/CodeGen/X86/widen_compare-1.ll b/test/CodeGen/X86/widen_compare-1.ll index 8e2005753bd..f37e764fd6a 100644 --- a/test/CodeGen/X86/widen_compare-1.ll +++ b/test/CodeGen/X86/widen_compare-1.ll @@ -7,12 +7,12 @@ define <2 x i16> @compare_v2i64_to_v2i16_unary(<2 x i16>* %src) nounwind { ; X86-LABEL: compare_v2i64_to_v2i16_unary: ; X86: # %bb.0: -; X86-NEXT: pcmpeqd %xmm0, %xmm0 +; X86-NEXT: movaps {{.*#+}} xmm0 = [65535,0,65535,0] ; X86-NEXT: retl ; ; X64-LABEL: compare_v2i64_to_v2i16_unary: ; X64: # %bb.0: -; X64-NEXT: pcmpeqd %xmm0, %xmm0 +; X64-NEXT: movaps {{.*#+}} xmm0 = [65535,65535] ; X64-NEXT: retq %val = load <2 x i16>, <2 x i16>* %src, align 4 %cmp = icmp uge <2 x i16> %val, %val