From: Craig Topper <craig.topper@intel.com>
Date: Sun, 13 Aug 2017 17:40:02 +0000 (+0000)
Subject: [AVX512] Correct isExtractSubvectorCheap so that it will return the correct answers... 
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=5c791157e86fc00b3af92b4db0f48900838379ba;p=llvm

[AVX512] Correct isExtractSubvectorCheap so that it will return the correct answers for extracting 128-bits from a 512-bit vector and for mask registers.

Previously it would not return true for extracting either of the upper quarters of a 512-bit registers.

For mask registers we support extracting anything from index 0. And otherwise we only support extracting the upper half of a register.

Differential Revision: https://reviews.llvm.org/D36638

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310794 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index f5040b8e0b3..04ee7121c7e 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -4579,7 +4579,13 @@ bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
   if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
     return false;
 
-  return (Index == 0 || Index == ResVT.getVectorNumElements());
+  // Mask vectors support all subregister combinations and operations that
+  // extract half of vector.
+  if (ResVT.getVectorElementType() == MVT::i1)
+    return Index = 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits() * 2) &&
+                         (Index == ResVT.getVectorNumElements()));
+
+  return (Index % ResVT.getVectorNumElements()) == 0;
 }
 
 bool X86TargetLowering::isCheapToSpeculateCttz() const {