From: Ivan Grokhotkov <ivan@espressif.com>
Date: Sun, 12 Aug 2018 22:11:32 +0000 (+0300)
Subject: soc/rtc: Force power on 8M clock if it is used to derive RTC slow clock
X-Git-Tag: v3.2-beta1~285^2~1
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=5bf36546379b55ba80313699a551104c7e29a8c9;p=esp-idf

soc/rtc: Force power on 8M clock if it is used to derive RTC slow clock
---

diff --git a/components/soc/esp32/rtc_sleep.c b/components/soc/esp32/rtc_sleep.c
index 041c2d1b6b..6b16aa2889 100644
--- a/components/soc/esp32/rtc_sleep.c
+++ b/components/soc/esp32/rtc_sleep.c
@@ -197,6 +197,12 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
 
     REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu);
 
+    if (REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL) == RTC_SLOW_FREQ_8MD256) {
+        REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
+    } else {
+        REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
+    }
+
     /* enable VDDSDIO control by state machine */
     REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE);
     REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en);