From: Simon Atanasyan <simon@atanasyan.com>
Date: Wed, 13 Mar 2019 14:22:58 +0000 (+0000)
Subject: [mips] Define `mov.d` instructions using `ABSS_M` multiclass. NFC
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=59c736bd3e6335ec8ddeecd9127f2453edc9e1c2;p=llvm

[mips] Define `mov.d` instructions using `ABSS_M` multiclass. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356051 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td
index f2648a7e8e4..0b03da9b5a6 100644
--- a/lib/Target/Mips/MipsInstrFPU.td
+++ b/lib/Target/Mips/MipsInstrFPU.td
@@ -550,12 +550,7 @@ let AdditionalPredicates = [NotInMicroMips] in {
   let isMoveReg = 1 in {
     def FMOV_S   : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
                    ABSS_FM<0x6, 16>, ISA_MIPS1;
-    def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
-                   ABSS_FM<0x6, 17>, ISA_MIPS1, FGR_32;
-    def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>,
-                   ABSS_FM<0x6, 17>, ISA_MIPS1, FGR_64 {
-                     let DecoderNamespace = "MipsFP64";
-    }
+    defm FMOV : ABSS_M<"mov.d", II_MOV_D>, ABSS_FM<0x6, 17>, ISA_MIPS1;
   } // isMoveReg
 }