From: Sanjay Patel <spatel@rotateright.com>
Date: Tue, 11 Oct 2016 13:36:07 +0000 (+0000)
Subject: [x86] update test to use FileCheck and auto-generate checks
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=5988ab8dc19ca9a5a73871b02bcbf7d0c4f837c6;p=llvm

[x86] update test to use FileCheck and auto-generate checks


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283876 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/X86/2008-02-14-BitMiscompile.ll b/test/CodeGen/X86/2008-02-14-BitMiscompile.ll
index 1983f1d19c6..259a3acd2db 100644
--- a/test/CodeGen/X86/2008-02-14-BitMiscompile.ll
+++ b/test/CodeGen/X86/2008-02-14-BitMiscompile.ll
@@ -1,8 +1,18 @@
-; RUN: llc < %s -march=x86 | grep and
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s
+
 define i32 @test(i1 %A) {
-	%B = zext i1 %A to i32		; <i32> [#uses=1]
-	%C = sub i32 0, %B		; <i32> [#uses=1]
-	%D = and i32 %C, 255		; <i32> [#uses=1]
-	ret i32 %D
+; CHECK-LABEL: test:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    andl $1, %eax
+; CHECK-NEXT:    negl %eax
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    retl
+;
+  %B = zext i1 %A to i32
+  %C = sub i32 0, %B
+  %D = and i32 %C, 255
+  ret i32 %D
 }