From: Tom Stellard <thomas.stellard@amd.com>
Date: Mon, 16 Nov 2015 17:23:23 +0000 (+0000)
Subject: Merging r243661:
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=594e6efc1ef1c1082862217a2a1d1c8f1f1fb040;p=llvm

Merging r243661:

------------------------------------------------------------------------
r243661 | Matthew.Arsenault | 2015-07-30 13:03:11 -0400 (Thu, 30 Jul 2015) | 6 lines

AMDGPU: Set SubRegIndex size and offset

I'm not sure what reasons the comment here could have
had for not setting these. Without these set, there is
an assertion hit during DWARF emission.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_37@253230 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/AMDGPURegisterInfo.td b/lib/Target/AMDGPU/AMDGPURegisterInfo.td
index 835a1464395..ba0490abee8 100644
--- a/lib/Target/AMDGPU/AMDGPURegisterInfo.td
+++ b/lib/Target/AMDGPU/AMDGPURegisterInfo.td
@@ -14,8 +14,7 @@
 let Namespace = "AMDGPU" in {
 
 foreach Index = 0-15 in {
-  // Indices are used in a variety of ways here, so don't set a size/offset.
-  def sub#Index : SubRegIndex<-1, -1>;
+  def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
 }
 
 def INDIRECT_BASE_ADDR : Register <"INDIRECT_BASE_ADDR">;