From: Hans Wennborg Date: Thu, 25 Jan 2018 15:28:01 +0000 (+0000) Subject: Merging r323369 and r323371: X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=57ea45a7084fe7220fc1b3dd2b00cdfb87c38eb1;p=llvm Merging r323369 and r323371: ------------------------------------------------------------------------ r323369 | aemerson | 2018-01-24 20:59:29 +0100 (Wed, 24 Jan 2018) | 4 lines [GlobalISel] Don't fall back to FastISel. Apparently checking the pass structure isn't enough to ensure that we don't fall back to FastISel, as it's set up as part of the SelectionDAGISel. ------------------------------------------------------------------------ ------------------------------------------------------------------------ r323371 | aemerson | 2018-01-24 21:35:37 +0100 (Wed, 24 Jan 2018) | 12 lines [AArch64][GlobalISel] Fall back during AArch64 isel if we have a volatile load. The tablegen imported patterns for sext(load(a)) don't check for single uses of the load or delete the original after matching. As a result two loads are left in the generated code. This particular issue will be fixed by adding support for a G_SEXTLOAD opcode in future. There are however other potential issues around this that wouldn't be fixed by a G_SEXTLOAD, so until we have a proper solution we don't try to handle volatile loads at all in the AArch64 selector. Fixes/works around PR36018. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@323434 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index befd797e75b..bd9fcfb5c1e 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -1380,8 +1380,10 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { FastISelFailed = false; // Initialize the Fast-ISel state, if needed. FastISel *FastIS = nullptr; - if (TM.Options.EnableFastISel) + if (TM.Options.EnableFastISel) { + DEBUG(dbgs() << "Enabling fast-isel\n"); FastIS = TLI->createFastISel(*FuncInfo, LibInfo); + } setupSwiftErrorVals(Fn, TLI, FuncInfo); diff --git a/lib/CodeGen/TargetPassConfig.cpp b/lib/CodeGen/TargetPassConfig.cpp index c90a93d7e24..6c91bdc1c52 100644 --- a/lib/CodeGen/TargetPassConfig.cpp +++ b/lib/CodeGen/TargetPassConfig.cpp @@ -717,6 +717,8 @@ bool TargetPassConfig::addCoreISelPasses() { if (EnableGlobalISel == cl::BOU_TRUE || (EnableGlobalISel == cl::BOU_UNSET && isGlobalISelEnabled() && EnableFastISelOption != cl::BOU_TRUE)) { + TM->setFastISel(false); + if (addIRTranslator()) return true; diff --git a/lib/Target/AArch64/AArch64InstructionSelector.cpp b/lib/Target/AArch64/AArch64InstructionSelector.cpp index b85b4e08299..2bb9e381073 100644 --- a/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -929,6 +929,12 @@ bool AArch64InstructionSelector::select(MachineInstr &I, return false; } + // FIXME: PR36018: Volatile loads in some cases are incorrectly selected by + // folding with an extend. Until we have a G_SEXTLOAD solution bail out if + // we hit one. + if (Opcode == TargetOpcode::G_LOAD && MemOp.isVolatile()) + return false; + const unsigned PtrReg = I.getOperand(1).getReg(); #ifndef NDEBUG const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI); diff --git a/test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll b/test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll new file mode 100644 index 00000000000..84d8faf62c8 --- /dev/null +++ b/test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll @@ -0,0 +1,10 @@ +; RUN: llc -mtriple=aarch64_be-- %s -o /dev/null -debug-only=isel -O0 2>&1 | FileCheck %s + +; This test uses big endian in order to force an abort since it's not currently supported for GISel. +; The purpose is to check that we don't fall back to FastISel. Checking the pass structure is insufficient +; because the FastISel is set up in the SelectionDAGISel, so it doesn't appear on the pass structure. + +; CHECK-NOT: Enabling fast-ise +define void @empty() { + ret void +} diff --git a/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll b/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll new file mode 100644 index 00000000000..9bda39c9fca --- /dev/null +++ b/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll @@ -0,0 +1,14 @@ +; RUN: llc -O0 -mtriple=aarch64-apple-ios -o - %s | FileCheck %s + +@g = global i16 0, align 2 +declare void @bar(i32) + +; Check that only one load is generated. We fall back to +define hidden void @foo() { +; CHECK-NOT: ldrh +; CHECK: ldrsh + %1 = load volatile i16, i16* @g, align 2 + %2 = sext i16 %1 to i32 + call void @bar(i32 %2) + ret void +}