From: Sanjay Patel <spatel@rotateright.com>
Date: Tue, 29 Nov 2016 19:15:27 +0000 (+0000)
Subject: [AArch64] add tests for bics; NFC
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=57d4f76dcd253ec916300f83a43c8e697527b4ae;p=llvm

[AArch64] add tests for bics; NFC


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288183 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/AArch64/bics.ll b/test/CodeGen/AArch64/bics.ll
new file mode 100644
index 00000000000..1c0c0793d36
--- /dev/null
+++ b/test/CodeGen/AArch64/bics.ll
@@ -0,0 +1,44 @@
+; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
+
+define i1 @andn_cmp(i32 %x, i32 %y) {
+; CHECK-LABEL: andn_cmp:
+; CHECK:       // BB#0:
+; CHECK-NEXT:    bics wzr, w1, w0
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
+;
+  %notx = xor i32 %x, -1
+  %and = and i32 %notx, %y
+  %cmp = icmp eq i32 %and, 0
+  ret i1 %cmp
+}
+
+; FIXME: Recognize a disguised bics.
+
+define i1 @and_cmp(i32 %x, i32 %y) {
+; CHECK-LABEL: and_cmp:
+; CHECK:       // BB#0:
+; CHECK-NEXT:    and w8, w0, w1
+; CHECK-NEXT:    cmp w8, w1
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
+;
+  %and = and i32 %x, %y
+  %cmp = icmp eq i32 %and, %y
+  ret i1 %cmp
+}
+
+define i1 @and_cmp_const(i32 %x) {
+; CHECK-LABEL: and_cmp_const:
+; CHECK:       // BB#0:
+; CHECK-NEXT:    mov w8, #43
+; CHECK-NEXT:    and w8, w0, w8
+; CHECK-NEXT:    cmp w8, #43
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
+;
+  %and = and i32 %x, 43
+  %cmp = icmp eq i32 %and, 43
+  ret i1 %cmp
+}
+