From: Diana Picus Date: Tue, 28 Feb 2017 12:13:58 +0000 (+0000) Subject: [ARM] GlobalISel: Add mapping for G_CONSTANT X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=568082bafef8bd1404425cae2694529990bfefb2;p=llvm [ARM] GlobalISel: Add mapping for G_CONSTANT Like G_FRAME_INDEX, G_CONSTANT has one register operand and one non-register operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296469 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/ARMRegisterBankInfo.cpp b/lib/Target/ARM/ARMRegisterBankInfo.cpp index 2d512428d6e..18ce7d454b8 100644 --- a/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -240,6 +240,7 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { ? &ARM::ValueMappings[ARM::DPR3OpsIdx] : &ARM::ValueMappings[ARM::SPR3OpsIdx]; break; + case G_CONSTANT: case G_FRAME_INDEX: OperandsMapping = getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr}); diff --git a/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir index 5b54ead6a63..355d723a3e7 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir @@ -10,6 +10,8 @@ define void @test_gep() { ret void } + define void @test_constants() { ret void } + define void @test_fadd_s32() #0 { ret void } define void @test_fadd_s64() #0 { ret void } @@ -225,6 +227,22 @@ body: | BX_RET 14, _, implicit %r0 ... --- +name: test_constants +# CHECK-LABEL: name: test_constants +legalized: true +regBankSelected: false +selected: false +# CHECK: registers: +# CHECK: - { id: 0, class: gprb } +registers: + - { id: 0, class: _ } +body: | + bb.0: + %0(s32) = G_CONSTANT 42 + %r0 = COPY %0(s32) + BX_RET 14, _, implicit %r0 +... +--- name: test_fadd_s32 # CHECK-LABEL: name: test_fadd_s32 legalized: true